Power7: IBM's Next-Generation Server Processor

Kalla, R.; Sinharoy, Balaram; Starke, William J.; Floyd, Michael S.

doi:10.1109/mm.2010.38

Cited by 206 publications

(55 citation statements)

References 6 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Using later parts in 32 nm (with approximately the same core transistor count of 75-80 M), and taking into account the graphic core power in Sandy Bridge [14], one obtains about ~50% power reduction, node-to-node (using parts i7-870S in 45 nm and i7-2960XM in 32 nm, with ~12W allocated for the graphic core running @ 650 MHz). To illustrate the technology benefit, we also use the IBM's POWER7 (in 45 nm [5]) and 7+ (in 32 nm [6]), ( Table 2). Chips in both technologies have the same area (576 mm 2 ) and the same total power.…”

Section: Technology Nodementioning

confidence: 99%

From 2D-planar to 3D-non-planar device architecture: A scalable path forward?

Shahidi

2013

Proceedings of the IEEE 2013 Custom Integrated Circuits Conference

View full text Add to dashboard Cite

The microelectronics industry is in the process of transitioning from 2D-planar devices to 3D-non-planar (FinFET). In this paper, a metric is developed to assess the impact of scaling and device performance on chip (circuit) power as it is migrated node-to-node. The impact of node migration is assessed at product level as it is moved from 32 nm (2D-planar) to 22 nm (3D-non-planar device). Some of the limitations of the existing 22 nm 3D-device is reviewed that may explain some of the short comings in the product performance. Going forward it is critical that in two areas the FinFET needs to be improved: Multi-V T implementation and move away from the tapered fin shape.

show abstract

Section: Technology Nodementioning

confidence: 99%

From 2D-planar to 3D-non-planar device architecture: A scalable path forward?

Shahidi

2013

Proceedings of the IEEE 2013 Custom Integrated Circuits Conference

View full text Add to dashboard Cite

show abstract

“…They make a step towards controlling, by e.g. turning off threads if resources are getting rare or by using adaptive power management features, see [8].…”

Section: State Of the Artmentioning

confidence: 99%

Design and evaluation of an adaptive real-time microprocessor

Bauer

Lohn

Betting

et al. 2013

2013 IEEE International Conference on Evolvable Systems (ICES)

View full text Add to dashboard Cite

Since most modern microprocessors are optimized for good average performance, their worst case performance is hard to predict. Therefore, the in time execution of real-time threads at any time is difficult to guarantee. So, in this paper we present an adaptive real-time microprocessor, which is fitted with a closed control loop. The controller is aware of the loss of performance due to various latency causing events at runtime and is able to respond to them by adapting the aimed throughput of each running thread. Afterwards, we evaluate our microprocessor with an embedded benchmark, discuss different parameters of the controller and show that a well-defined performance can be guaranteed by the use of control theory.

show abstract

“…BG/P has many enhanced features such as support for multithreading but the system's general architecture is similar. The next BG to appear in the market is based on the latest IBM Power 7 microprocessor [13]. Power 7 mixes both multithreading and multi-core on a chip that has eight cores and supports up to four thread per core to give 32-threads capability multithreaded applications.…”

Section: Ibm Blue Gene/lmentioning

confidence: 99%

Hierarchical-based parallel technique for HMM 3D MRI brain segmentation algorithm

El-Moursy

Saif

Younis

2012

International Journal of Parallel, Emergent and Distributed Sys

View full text Add to dashboard Cite

This paper proposes a hidden Markov model (HMM) algorithm for 3D MRI brain segmentation using a hierarchical/multi-level parallel implementation. The new technique is implemented using standard message passing interface (MPI). Two platforms are used to test the proposed technique namely PC-cluster system and IBM Blue Gene (BG)/L system. On PC-cluster system, hierarchical-based parallel HMM algorithm achieves a twofold speedup on a three nodes cluster and a threefold speedup on a six nodes cluster. Communication overhead and data dependency nullify any speedup beyond six nodes. On IBM BG/L system, the high-speed communication network and optimised MPI allow more efficient processing nodes utilisation although the algorithm data dependency limits the net speedup achieved.

show abstract

Power7: IBM's Next-Generation Server Processor

Cited by 206 publications

References 6 publications

From 2D-planar to 3D-non-planar device architecture: A scalable path forward?

From 2D-planar to 3D-non-planar device architecture: A scalable path forward?

Design and evaluation of an adaptive real-time microprocessor

Hierarchical-based parallel technique for HMM 3D MRI brain segmentation algorithm

Contact Info

Product

Resources

About