POWER2 instruction cache unit

Barreh, J. I.; Golla, Robert; Arimilli, L. B.; Jordan, P. J.

doi:10.1147/rd.385.0537

Cited by 3 publications

(1 citation statement)

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“…The new P0WER2™ workstations [1][2][3][4] of the RISC System/6000® (RS/6000) family of processors provide multiple fixed-point units (FXUs) and floating-point units (FPUs) which can work in parallel if there are no dependencies. We call this functional parallelism.…”

Section: Introductionmentioning

confidence: 99%

Exploiting functional parallelism of POWER2 to design high-performance numerical algorithms

1994

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We describe the algorithms and architecture approach to produce high-performance codes for numerically intensive computations. In this approach, for a given computation, we design algorithms so that they perform optimally when run on a target machine-in this case, the new P0WER2™ machines from the RS/6000 family of RISC processors. The algorithmic features that we emphasize are functional parallelism, cache/register blocking, algorithmic prefetching, loop unrolling, and algorithmic restructuring. The architectural features of the P0WER2 machine that we describe and that lead to high performance are multiple functional units, high bandwidth between registers, cache, and memory, a large number of fixed-and floating-point registers, and a large cache and TLB (translation lookaside buffer). The paper gives two examples that illustrate how the algorithms and architectural features Interplay to produce high-performance codes. They are BLAS (basic linear algebra subroutines) and narrow-band matrix routines. These routines are included in ESSL (Engineering and Scientific Subroutine Library); an overview of ESSL is also given in the paper.

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Section: Introductionmentioning

confidence: 99%

Exploiting functional parallelism of POWER2 to design high-performance numerical algorithms

1994

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POWER2: performance measurement and analysis of TPC-C

Franklin

Welbon

Proceedings of COMPCON '94

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POWER2: Next generation of the RISC System/6000 family

White

Dhawan

1994

IBM J. Res. & Dev.

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Next generation of the RlSC System/6000 family by S. W. White S. Dhawan Since its announcement, the IBM RISC System/6000@ processor has characterized the aggressive instruction-level parallelism approach to achieving performance. Recent enhancements to the architecture and implementation provide greater superscalar capability. This paper describes the architectural extensions which improve storage reference bandwidth, allow hardware square-root computation, and speed floating-point-to-integer conversion. The implementation, which exploits these extensions and doubles the number of functional units, is also described. A comparison of performance results on a variety of industry standard benchmarks demonstrates that superscalar capabilities are an attractive alternative to aggressive clock rates.

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POWER2 instruction cache unit

Cited by 3 publications

References 1 publication

Exploiting functional parallelism of POWER2 to design high-performance numerical algorithms

Exploiting functional parallelism of POWER2 to design high-performance numerical algorithms

POWER2: performance measurement and analysis of TPC-C

POWER2: Next generation of the RISC System/6000 family

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