Exploiting functional parallelism of POWER2 to design high-performance numerical algorithms

Abstract

We describe the algorithms and architecture approach to produce high-performance codes for numerically intensive computations. In this approach, for a given computation, we design algorithms so that they perform optimally when run on a target machine-in this case, the new P0WER2™ machines from the RS/6000 family of RISC processors. The algorithmic features that we emphasize are functional parallelism, cache/register blocking, algorithmic prefetching, loop unrolling, and algorithmic restructuring. The architectural features of the P0WER2 machine that we describe and that lead to high performance are multiple functional units, high bandwidth between registers, cache, and memory, a large number of fixed-and floating-point registers, and a large cache and TLB (translation lookaside buffer). The paper gives two examples that illustrate how the algorithms and architectural features Interplay to produce high-performance codes. They are BLAS (basic linear algebra subroutines) and narrow-band matrix routines. These routines are included in ESSL (Engineering and Scientific Subroutine Library); an overview of ESSL is also given in the paper.

Cache-optimal algorithms for option pricing

“…For computations, where data is reused many times, this technique reduces memory traffic to slower memories in the hierarchy [Hennessy and Patterson 2007]. The cache blocking technique has been extensively applied to linear algebra applications [Dongarra et al 1990;Anderson et al 1999;Kågström et al 1998;Gupta et al 1998;Goto and van de Geijn 2008;Agarwal et al 1994a]. Since accessing data from a slower memory is expensive, an algorithm that rarely goes to slower memory performs better.…”

Towards an accurate performance modeling of parallel sparse factorization

“…For the DGEMM routine, we have found that a 4 by 2 unrolling matches well our estimation of number of loads. Note that this is also the unrolling level used on the IBM POWER2 [1], which ensures that the multiple functional units are fully utilized.…”

The design, implementation, and evaluation of a symmetric banded linear solver for distributed-memory parallel computers

“…The peak floating-point performance of POWER2-based nodes is 266 million operations per second, thanks to two floating-point functional units that can each execute a multiply-add operation in every cycle. The high bandwidth between the register file and the cache, as well as the high bandwidth of the main memory system, enable the nodes to achieve near-peak performance on many dense-matrix operations [Agarwal et al 1994], including all the block operations that our solver uses. SP2 nodes with 128-and 256-bit-wide buses have an even higher main memory bandwidth, which increases the performance of both intraprocessor and interprocessor data transfers.…”

“…Communication between the functional units of the same CPU is fast and incurs no overhead. The primitive block operations that our solver uses therefore take advantage of the multiple functional units, so they are parallelized as well by using so-called functional parallelism [Agarwal et al 1994] at the instruction level.…”