Power Reduction by Clock Gating Technique

Srinivasan, Nandita; Prakash, Navamitha S.; Shalakha, D; Sivaranjani, D.; Lakshmi, G Swetha Sri; Sundari, B. Bala Tripura

doi:10.1016/j.protcy.2015.10.075

Cited by 28 publications

(12 citation statements)

References 5 publications

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“…Clock gating [40] Adds logic to the circuit to prune the clock tree Works to disable portions of the circuitry, saving switching power 5 Wireless Communications and Mobile Computing voltage and frequency scaling (DVFS) are popular approaches to logic device optimization [64]. DPM puts the processor in sleep mode to save power when there is no need for computation while DVFS is employed to find optimal voltage and frequency from some discrete frequency and voltage settings based on load requirements.…”

Section: Reduces Leakage Powermentioning

confidence: 99%

Energy Efficient Design Techniques in Next-Generation Wireless Communication Networks: Emerging Trends and Future Directions

Ogbebor

Imoize

Atayero

2020

Wireless Communications and Mobile Computing

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The projected rise in wireless communication traffic has necessitated the advancement of energy-efficient (EE) techniques for the design of wireless communication systems, given the high operating costs of conventional wireless cellular networks, and the scarcity of energy resources in low-power applications. The objective of this paper is to examine the paradigm shifts in EE approaches in recent times by reviewing traditional approaches to EE, analyzing recent trends, and identifying future challenges and opportunities. Considering the current energy concerns, nodes in emerging wireless networks range from limited-energy nodes (LENs) to high-energy nodes (HENs) with entirely different constraints in either case. In view of these extremes, this paper examines the principles behind energy-efficient wireless communication network design. We then present a broad taxonomy that tracks the areas of impact of these techniques in the network. We specifically discuss the preponderance of prediction-based energy-efficient techniques and their limits, and then discuss the trends in renewable energy supply systems for future networks. Finally, we recommend more context-specific energy-efficient research efforts and cross-vendor collaborations to push the frontiers of energy efficiency in the design of wireless communication networks.

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Section: Reduces Leakage Powermentioning

confidence: 99%

Energy Efficient Design Techniques in Next-Generation Wireless Communication Networks: Emerging Trends and Future Directions

Ogbebor

Imoize

Atayero

2020

Wireless Communications and Mobile Computing

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“…Clock gating is an effective technique used mostly in the SoC design to save dynamic power, where the peculiar clock will be shut down when it is not required [6]. Clock gating can be divided into two approaches, which one of them is RTL clock gating.…”

Section: Gated Clock Conversionmentioning

confidence: 99%

Timing violation reduction in the FPGA prototyped design using failed path fixes and time borrowing techniques

Savugathali

Mustapa

Razali

et al. 2019

IJEECS

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<span>A fascinating property of a latch-based design is that the combinational path delay is allowed to be longer than the clock cycle as it can borrow time from the shorter paths in the subsequent logic states. Time borrowing technique is a common method used to satisfy timing violation in an FPGA prototyped design. The purpose of this paper is to review the current methodology involved in SoC design prototyping using a Synopsys Protocompiler and HAPS-80 platform and propose an approach by fixing the failed path in a latch due to the gated clock conversion (GCC) process during the synthesis stage which could lead to the timing violation. Two techniques are applied in this paper namely time borrowing technique and our proposed technique, Failed Path Fixes to reduce the timing violation in the FPGA prototyped design. The result shows that the applied techniques are able to close the timing violation in the design with an average of 90% improvement.</span>

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“…By adopting the clock-gating approach, power dissipation can be reduced significantly, lowering not only the switching activity at the function unit level, but also the switched capacitive load on the clock distribution network. Here the clock gating [10] is implemented using AND gates. Fig.…”

Section: Clock Gating Techniquementioning

confidence: 99%

Dynamic Power Reduction of Digital Circuits by ClockGating

Dewre¹,

Mandliya²

2017

IJERA

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In this paper we have presented clock gating process for low power VLSI (very large scale integration) circuit design. Clock gating is one of the most quite often used systems in RTL to shrink dynamic power consumption without affecting the performance of the design. One process involves inserting gating requisites in the RTL, which the synthesis tool translates to clock gating cells in the clock-path of a register bank. This helps to diminish the switching activity on the clock network, thereby decreasing dynamic power consumption within the design. Due to the fact the translation accomplished via the synthesis tool is solely combinational; it is referred to as combinational clock gating. This transformation does not alter the behavior of the register being gated.

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Power Reduction by Clock Gating Technique

Cited by 28 publications

References 5 publications

Energy Efficient Design Techniques in Next-Generation Wireless Communication Networks: Emerging Trends and Future Directions

Energy Efficient Design Techniques in Next-Generation Wireless Communication Networks: Emerging Trends and Future Directions

Timing violation reduction in the FPGA prototyped design using failed path fixes and time borrowing techniques

Dynamic Power Reduction of Digital Circuits by ClockGating

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