Power/Performance Trade-Offs in Real-Time SDRAM Command Scheduling

Abstract

Abstract-Real-time safety-critical systems should provide hard bounds on an applications' performance. SDRAM controllers used in this domain should therefore have a bounded worst-case bandwidth, response time, and power consumption. Existing works on real-time SDRAM controllers only consider a narrow range of memory devices, and do not evaluate how their schedulers' performance varies across memory generations, nor how the scheduling algorithm influences power usage. The extent to which the number of banks used in parallel to serve a request impacts performance is also unexplored, and hence there are gaps in the tool set of a memory subsystem designer, in terms of both performance analysis, and configuration options. This article introduces a generalized close-page memory command scheduling algorithm that uses a variable number of banks in parallel to serve a request. To reduce the schedule length for DDR4 memories, we exploit bank grouping through a pairwise bank-group interleaving scheme. The algorithm is evaluated using an ILP formulation, and provides schedules of optimal length for most of the considered LPDDR, DDR2, DDR3, LPDDR2, LPDDR3 and DDR4 devices. We derive the worst-case bandwidth, power and execution time for the same set of devices, and discuss the observed trade-offs and trends in the scheduler-configuration design space based on these metrics, across memory generations.

Modeling and Verification of Dynamic Command Scheduling for Real-Time Memory Controllers

“…Since memory controllers have common components, e.g., the timing constraint counters and command bus, the corresponding TA can be reused when modeling other memory controllers. 4) Is easily adapted to different memory generations (e.g., DDR3 and LPDDR3) by replacing the timing constraint values for the specific memory device [8]. The Source in Fig.…”

“…For each transaction size, BI and BC are configured to achieve the lowest execution time [23]. BS is aligned with BI to simplify the physical address decoding [8]. When the memory mapping is finished, the number (i.e., NrTrans) of transactions in the back-end is increased and command scheduling is triggered.…”

“…The memory map configuration (i.e., BI and BC) of each transaction size is chosen to achieve the lowest execution time and the highest memory bandwidth, where more banks are interleaved when possible to exploit bank parallelism. The configured (BI, BC) for these sizes are hence (1, 1), (2, 1), (4,1), (4,2), and (4, 4) [8], respectively. Note that transactions with 128 bytes and 256 bytes use (4,2) and (4,4) instead of (8, 1) and (8,2) because of the tFAW constraint that leads to larger execution time with BI = 8.…”

Mode-controlled data-flow modeling of real-time memory controllers

“…These commands are sequentially buffered in the queue per bank. This repeats BI times for all the required consecutive banks, and the data access granularity is BI ×BC ×BL words [17]. By varying BI and BC, different transaction sizes are supported [4].…”

“…The size is mapped to BI and BC, while the physical address gives the starting bank (b s ). For example, when a system only generates 64 byte read and write transactions, e.g., the L2 cache line size is 64 bytes for all cores, the most efficient configuration of BI=4 and BC=1 is used to access a DDR3 SDRAM with a 16-bit data bus [17]. Since DDR3 SDRAMs have 8 banks, the transactions may either interleave consecutively over Bank 0 to Bank 3 or Bank 4 to Bank 7 for alignment reasons [17].…”