Power-Performance Simulation and Design Strategies for Single-Chip Heterogeneous Multiprocessors

ACM Trans. Des. Autom. Electron. Syst.

2008

Single Chip Heterogeneous Multiprocessors executing a wide variety of software are increasingly common in consumer electronics. Because of the mix of real-time and best effort software across the entire chip, a key design element of these systems is the choice of scheduling strategy. Without task migration, the benefits of single chip processing cannot be fully realized. Previously, high-level modeling environments have not been capable of modeling asynchronous events such as interrupts and preemptive scheduling while preserving the performance benefits of high level simulation. This paper shows how extensions to Modeling Environment for Software and Hardware (MESH) enable precise modeling of these asynchronous events while running more than 1000 times faster than cycle-accurate simulation. We discuss how we achieved this and illustrate its use in modeling preemptive scheduling. We evaluate the potential of migrating running tasks between processors to improve performance in a multimedia cell phone example. We show that by allowing schedulers to rebalance processor loads as new tasks arrive significant performance gains can be achieved over statically partitioned and dynamic scheduling approaches. In our example, we show that system response time can be improved by as much as 1.96 times when a preemptive migratory scheduler is used, despite the overhead incurred by scheduling tasks across multiple processors and transferring state during the migration of running tasks. The contribution of this work is to provide a framework for evaluating preemptive scheduling policies and task migration in a high level simulator, by combining the new ability to model interrupts with dramatically increased efficiency in the high-level modeling of scheduling and commuincation MESH already provides.

Section: Overview Of Meshmentioning

confidence: 95%

“…It can also provide equivalent sets of resource consumption, to specify how hardware features such as floating point support would affect its performance. This ability can be applied successfully to divisions as fine as individual instruction types [Meyer et al 2005], though this is usually unnecessary.…”

Section: Task Migration and Pre-emptive Schedulingmentioning

confidence: 99%

Interrupt modeling for efficient high-level scheduler design space exploration

Johnson

ACM Trans. Des. Autom. Electron. Syst.

2008

“…At design time, for each unique workload mode, we dedicate an optimization profile that stores the optimal system parameters such as frequency/voltage of each processor as well as where each task can be run. Other techniques such as Dynamic Voltage and Frequency Scaling (DVFS) [12], [13], [14] and processor power state management (on, off, or idle) can be used for reducing energy consumption. Further, different scheduling/mapping mechanisms can also be customized according to the identified workload mode.…”

Section: Workload Modesmentioning

confidence: 99%

Capacity metric for chip heterogeneous multiprocessors

Otoom

Proceedings of the Seventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis

2011

The primary contribution of this thesis is the development of a new performance metric, Capacity, which evaluates the performance of Chip Heterogeneous Multiprocessors (CHMs) that process multiple heterogeneous channels. Performance metrics are required in order to evaluate any system, including computer systems. A lack of appropriate metrics can lead to ambiguous or incorrect results, something discovered while developing the secondary contribution of this thesis, that of workload modes for CHMsor Workload Specific Processors (WSPs).For many decades, computer architects and designers have focused on techniques that reduce latency and increase throughput. The change in modern computer systems built around CHMs that process multi-channel communications in the service of single users calls this focus into question. Modern computer systems are expected to integrate tens to hundreds of processor cores onto single chips, often used in the service of single users, potentially as a way to access the Internet. Here, the design goal is to integrate as much functionality as possible during a given time window. Without the ability to correctly identify optimal designs, not only will the best performing designs not be found, but resources will be wasted and there will be a lack of insight to what leads to better performing designs. To address performance evaluation challenges of the next generation of computer systems, such as multicore computers inside of cell phones, we found that a structurally different metric is needed and proceeded to develop such a metric.In contrast to single-valued metrics, Capacity is a surface with dimensionality related to the number of input streams, or channels, processed by the CHM. We develop some fundamental Capacity curves in two dimensions and show how Capacity shapes reveal interaction of not only programs and data, but the interaction of multiple data streams as they compete for access to resources on a CHM as well. For the analysis of Capacity surface shapes, we propose the development of a demand characterization method in which its output is in the form of a surface. By overlaying demand surfaces over Capacity iii surfaces, we are able to identify when a system meets its demands and by how much.Using the Capacity metric, computer performance optimization is evaluated against workloads in the service of individual users instead of individual applications, aggregate applications, or parallel applications. Because throughput was originally derived by drawing analogies between processor design and pipelines in the automobile industry, we introduce our Capacity metric for CHMs by drawing an analogy to automobile production, signifying that Capacity is the successor to throughput. By developing our Capacity metric, we illustrate how and why different processor organizations cannot be understood as being better performers without both magnitude and shape analysis in contrast to other metrics, such as throughput, that consider only magnitude.In this work, we make the following major ...

“…For simulation, we used a C-based simulation tool called MESH (Modeling Environment for Software and Hardware), which permits performance and power evaluation when threads execute on sets of heterogeneous resources under a variety of custom schedulers [30]. Energy consumption is calculated as the summation of the power consumed during ON and IDLE times [30].…”

Section: Table 1 Processing Elements For Sets a B And Cmentioning

confidence: 99%

Holistic design and caching in mobile computing

Otoom

Proceedings of the 6th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis

2008

We utilize application trends analysis, focused on webpage content, in order to examine the design of mobile computers more holistically. We find that both Internet bandwidth and processing local to the computing device is being wasted by re-transmission of formatting data. By taking this broader view, and separating Macromedia Flash content into raw data and its packaging, we show that performance can be increased by 84%, power consumption can be decreased by 71%, and communications bandwidth can be saved by an order of magnitude.