Holistic design and caching in mobile computing

Otoom, Mwaffaq; Paul, JoAnn M.

doi:10.1145/1450135.1450161

Cited by 4 publications

(3 citation statements)

References 16 publications

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“…Thus, while the MPEG application persists in the system for a long period of time, optimization of the whole system requires consideration of the data being processed. Also, webpage have different time granularities during which the content updates [1,19]. These updates may result in on chip optimizations.…”

Section: Workload Specific Processors (Wsps)mentioning

confidence: 99%

Workload Mode Identification for Chip Heterogeneous Multiprocessors

Otoom

Paul

2011

Int J Parallel Prog

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With the potential for tens to hundreds of processing elements on future single chip multicore designs also comes the potential to execute a wider variety of input streams, or workloads. At the same time, the trend is for single users to utilize an entire single chip multicore computer. A central challenge for these computers is how to model and identify persistent changes in the input stream, or workload modes. Computer architects often model single program phases as Markov chains. We define workload modes and analyze and evaluate two modeling techniques, a Workload Classification Model (WCM) and a Hidden Markov Model (HMM). We include experimentation on a cell phone example, illustrating how WCM is, on average, 34 times more time efficient and 83% more space efficient than HMM, while improving overall performance by an average of 191% and being, on average, 56% more energy efficient. We found that even sub-optimal use of WCM can outperform HMM, further supporting the need for design time workload models. Our main contribution is to show how the design of single user multicore architecture to models of workloads that arise from single user usage patterns will be necessary as the complexity of applications and architectures grows. Thus, we advocate Workload Specific Processors as a new means of orienting single-user chip heterogeneous multiprocessors.

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Section: Workload Specific Processors (Wsps)mentioning

confidence: 99%

Workload Mode Identification for Chip Heterogeneous Multiprocessors

Otoom

Paul

2011

Int J Parallel Prog

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“…Thus, while the MPEG application persists in the system for a long period of time, optimization of the whole system requires consideration of the data being processed. Also, webpages have different time granularities, during which the content updates [46], [48]. These updates may result in on-chip optimizations.…”

Section: Figure 18: Application Arrival Timing Of Different Performanmentioning

confidence: 99%

“…This type of webpage has different requirements than that of the second scenario, in which the businesswoman accesses financial webpages most of the time. These differences do not just exist in the size and complexity of content, type of content, and number of jobs, but also in the arrival timing of data that affects the response of the system to the frequency of changes in the input stream [48].…”

Section: Example: Usage Scenariosmentioning

confidence: 99%

Capacity metric for chip heterogeneous multiprocessors

Otoom

Paul

2011

Proceedings of the Seventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis

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The primary contribution of this thesis is the development of a new performance metric, Capacity, which evaluates the performance of Chip Heterogeneous Multiprocessors (CHMs) that process multiple heterogeneous channels. Performance metrics are required in order to evaluate any system, including computer systems. A lack of appropriate metrics can lead to ambiguous or incorrect results, something discovered while developing the secondary contribution of this thesis, that of workload modes for CHMsor Workload Specific Processors (WSPs).For many decades, computer architects and designers have focused on techniques that reduce latency and increase throughput. The change in modern computer systems built around CHMs that process multi-channel communications in the service of single users calls this focus into question. Modern computer systems are expected to integrate tens to hundreds of processor cores onto single chips, often used in the service of single users, potentially as a way to access the Internet. Here, the design goal is to integrate as much functionality as possible during a given time window. Without the ability to correctly identify optimal designs, not only will the best performing designs not be found, but resources will be wasted and there will be a lack of insight to what leads to better performing designs. To address performance evaluation challenges of the next generation of computer systems, such as multicore computers inside of cell phones, we found that a structurally different metric is needed and proceeded to develop such a metric.In contrast to single-valued metrics, Capacity is a surface with dimensionality related to the number of input streams, or channels, processed by the CHM. We develop some fundamental Capacity curves in two dimensions and show how Capacity shapes reveal interaction of not only programs and data, but the interaction of multiple data streams as they compete for access to resources on a CHM as well. For the analysis of Capacity surface shapes, we propose the development of a demand characterization method in which its output is in the form of a surface. By overlaying demand surfaces over Capacity iii surfaces, we are able to identify when a system meets its demands and by how much.Using the Capacity metric, computer performance optimization is evaluated against workloads in the service of individual users instead of individual applications, aggregate applications, or parallel applications. Because throughput was originally derived by drawing analogies between processor design and pipelines in the automobile industry, we introduce our Capacity metric for CHMs by drawing an analogy to automobile production, signifying that Capacity is the successor to throughput. By developing our Capacity metric, we illustrate how and why different processor organizations cannot be understood as being better performers without both magnitude and shape analysis in contrast to other metrics, such as throughput, that consider only magnitude.In this work, we make the following major ...

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Performance analysis of a 2-tier caching proxy system for mobile RESTful services

Ollite

Mohamudally

2015

IEEE EUROCON 2015 - International Conference on Computer as a Tool (EUROCON)

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Holistic design and caching in mobile computing

Cited by 4 publications

References 16 publications

Workload Mode Identification for Chip Heterogeneous Multiprocessors

Workload Mode Identification for Chip Heterogeneous Multiprocessors

Capacity metric for chip heterogeneous multiprocessors

Performance analysis of a 2-tier caching proxy system for mobile RESTful services

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