Power Optimized Transceivers for Future Switched Networks

Abstract

Network equipment power consumption is under increased scrutiny. To understand and decompose transceiver power consumption, we have created a toolkit incorporating a library of transceiver circuits in 45-nm CMOS and MOS current mode logic (MCML) and characterize power consumption using representative network traffic traces with digital synthesis and SPICE tools. Our toolkit includes all the components required to construct a library of different transceivers: line coding, frame alignment, channel bonding, serialization and deserialization, clock-data recovery, and clock generation. For optical transceivers, we show that photonic components and front end drivers only consume a small fraction (<22%) of total serial transceiver power. This implies that major reductions in optical transceiver power can only be obtained by paying attention to the physical layer circuits such as clock recovery and serial-parallel conversions. We propose a burst-mode physical layer protocol suitable for optically switched links that retains the beneficial transmission characteristics of 8b/10b, but, even without power gating and voltage controlled oscillator power optimization, reduces the power consumption during idle periods by 29% compared with a conventional 8b/10b transceiver. We have made the toolkit available to the community at large in the hope of stimulating work in this field.

Attojoule Optoelectronics for Low-Energy Information Processing and Communications

“…Energy per bit References and notes Wireless data 10 -30μJ [31] Internet: access 40 -80nJ [8]; (a),(b) Internet: routing 20nJ [9]; (c) Internet: optical WDM links 3nJ [32]; (d) Reading DRAM 5pJ [5]; (e) Communicating off chip 1 -20 pJ [5], [15], [16] Data link multiplexing and timing circuits ~ 2 pJ [24] Communicating across chip 600 fJ [5]; (f) Floating point operation 100fJ [5]; (g) Energy in DRAM cell 10fJ [33]; (h) Switching CMOS gate ~50aJ -3fJ [4], [6], [34], [35]; (i) 1 electron at 1V, or 1 photon @1eV 0.16aJ (160zJ) WDM -wavelength division multiplexing DRAM -dynamic random-access memory CMOS -complementary metal-oxide-semiconductor transistor (a) Uses projections to 2016 from [8] (b) Presumes wired connections (optical or electrical) to the network (c) Total for 20 "hops" per internet connection, and derating energies from the 2008 numbers in [9] using a factor of 0.74 per year (from [8]) for improved electronics energy efficiency. (d) Total for 20 "hops" per internet connection, and using projections to 2016 in [32] (e) Rounded sum of the DRAM access and interface energies as projected for 2017 in [5], for off-chip DRAM (f) Based on 2017 projects in [5] for a 10mm line on the chip (g) Double-precision fused multiply-add (floating-point) operation using the projection in [5] of ~ 6.5 pJ in 2017 for this 64-bit operation to calculate energy per bit.…”

“…12 Because the wavelength of light (in free space) λ = c/ν and the photon energy in electron volts, hν eV is the energy hν in joules divided by the magnitude of the electronic charge e, then hν eV = hc/eλ ≅1. 24 We can also think of this process in terms of optical energies, rather than powers; indeed, we may well be operating with a circuit more like that of Fig. 3(c), which has no load resistor 16 .…”

Low power optical transceivers for switched interconnect networks

“…In order to investigate the energy characteristics of integrated optical transceivers, we have carried out a characterization of transceiver architectures by design and synthesis of a variety of transceiver circuit blocks [18], [19]. The models created as part of this work are freely [20], including spice models, optimization scripts and Verilog hardware description language code which can be synthesized with any CMOS technology library.…”

“…For CMOS circuits, a traditional coarse-grained power-switching technique, consisting of header pMOS transistors shared across the entire CMOS block was used to reduce area and power overheads. Figure 3 shows contribution of individual components constituting 10 Gb/s 64B66B-based NRZ transceiver to the total power consumption [19]. For the front end circuits, we use the figures obtained in a recent demonstration of record low power 10 Gb/s silicon photonic components [16].…”

Current-mode circuit-level technique to design variation-aware nanoscale summing circuit for ultra-low power applications

“…Researches in the past are the evidence for the same. Low-swing dc-dc converter exhibits reduced (27.9 %) power dissipation as compared to a standard full-swing dc-dc converter (Kursun et al 2004;Audzevich et al 2014). Also, various techniques to reduce power consumption in domino logic circuits by lowering the voltage swing are presented in (Liu and Kursun 2006;Rjoub et al 1998;Friedman 2002, 2005).…”