Power Optimized ALU for Efficient Datapath

Abstract

With the scaling of technology and the need for high performance and more functionality, power dissipation becomes a major bottleneck for microprocessor systems design. Also clock power can be significant in high performance systems. In this paper, a low power ALU for efficient datapath is proposed. In ALU, based on the observation, that while one functional unit is working other functional units remain idle, but they are connected to clock and all units dissipating significant amount of power. By using clock gating technique, a significant amount of power saving can be achieved at high frequency operations. Functionality of proposed ALU implemented on FPGA is tested using Xilinx tool. Power analysis is carried out using Xilinx's Xpower analysis tool. It is found that designed ALU is dissipating a power of 24mw when it is operated at a clock frequency of 15MHz and supply voltage of 2.4V under load current of 4.8mA General TermsArchitecture, Low power.

Energy efficient implementation of 16-Bit ALU using block enabled clock gating technique

“…The glitches are observed for a negative edge triggered when AND gate CG is used and also for a counter when the latch has negative output. As a solution to these problems [4] proposes a new approach for CG using negative and positive latches. The functional unit of ALU contains the control unit and the datapath.…”