Power optimization techniques for associative processors

Yantır, Hasan Erdem; Eltawil, Ahmed M.; Niar, Smaïl; Kurdahi, Fadi

doi:10.1016/j.sysarc.2018.08.006

Cited by 4 publications

(5 citation statements)

References 10 publications

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“…A low-power, sub-ns sense amplifier design in [48] is employed in the matching circuit of CAM. For energy reduction, the proposed techniques in [38] where a compare operation is done at most four columns. For this reason, the general-purpose memory models like CACTI [49] are not used.…”

Section: Discussionmentioning

confidence: 99%

“…The operation is used two times to get the absolute value of input activation and convert the multiplication result to its original sign. Instead of using traditional absolute value operation where the result is written to another place, the in-place absolute value operation is proposed by utilizing the hardware optimization in [38] where the result is written in the same place as the operand. Table I shows these two LUTs for absolute value operations performed as bit-wise.…”

Section: B Cam Optimizationmentioning

confidence: 99%

“…7: Percentage of logic-0 in unsigned binary representation of the filter weights for 18 pre-trained CNNs (i.e., 1-k/m where m is the total bitwidth and k is the number of logic-1s) sets the R as the reverse of A for the remaining bits. The approach in [38] provides a mechanism which excludes the matched rows in the next compare cycle within a LUT pass, therefore releases the requirement for LUT ordering as well as it avoids the miswrites during a LUT pass. Table II shows the comparison of the proposed operation with the previous version.…”

Section: B Cam Optimizationmentioning

confidence: 99%

See 2 more Smart Citations

IMCA: An Efficient In-Memory Convolution Accelerator

Yantır

Eltawil

Salama

2021

IEEE Trans. VLSI Syst.

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Traditional convolutional neural network (CNN) architectures suffer from two bottlenecks; computational complexity and memory access cost. In this study, an efficient in-memory convolution accelerator (IMCA) is proposed based on associative in-memory processing to alleviate these two problems directly. In the IMCA, the convolution operations are directly performed inside the memory as in-place operations. The proposed memory computational structure allows for a significant improvement in computational metrics, namely, TOPS/W. Furthermore, due to its unconventional computation style, the IMCA can take advantage of many potential opportunities such as constant multiplication, bit-level sparsity, and dynamic approximate computing, which, while supported by traditional architectures, require extra overhead to exploit, thus reducing any potential gains. The proposed accelerator architecture exhibits a significant efficiency in terms of area and performance, achieving around 0.65 GOPS and 1.64 TOPS/W at 16-bit fixed-point precision with an area less than 0.25 mm 2 .

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Section: Discussionmentioning

confidence: 99%

Section: B Cam Optimizationmentioning

confidence: 99%

Section: B Cam Optimizationmentioning

confidence: 99%

See 1 more Smart Citation

IMCA: An Efficient In-Memory Convolution Accelerator

Yantır

Eltawil

Salama

2021

IEEE Trans. VLSI Syst.

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“…The interconnection matrix is a basic circuit-switched matrix which used to communicate with other APs as column parallel fashion. The architecture can also incorporate low-power mechanisms such as selective compare, where within a lookup table (LUT) pass, the matched rows are not precharged again since it is not possible to get another match in this row [35]. As the most important part of the CAM array, the cells can either be implemented by traditional SRAM memory or alternatively by emerging non-volatile memories such as memristor (ReRAM) or STT-RAM.…”

Section: Associate Processormentioning

confidence: 99%

“…Each entry corresponds to a combination of different Cr, B, A. Even though there is a total of eight (2 3 ) combinations, only four of them are used since others have no effect on the operation [35]. In each CAM of the figure, the key value from the compare column of the LUT is searched in the masked columns of the CAM.…”

Section: Content Addressablementioning

confidence: 99%

Efficient Acceleration of Stencil Applications through In-Memory Computing

2020

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The traditional computer architectures severely suffer from the bottleneck between the processing elements and memory that is the biggest barrier in front of their scalability. Nevertheless, the amount of data that applications need to process is increasing rapidly, especially after the era of big data and artificial intelligence. This fact forces new constraints in computer architecture design towards more data-centric principles. Therefore, new paradigms such as in-memory and near-memory processors have begun to emerge to counteract the memory bottleneck by bringing memory closer to computation or integrating them. Associative processors are a promising candidate for in-memory computation, which combines the processor and memory in the same location to alleviate the memory bottleneck. One of the applications that need iterative processing of a huge amount of data is stencil codes. Considering this feature, associative processors can provide a paramount advantage for stencil codes. For demonstration, two in-memory associative processor architectures for 2D stencil codes are proposed, implemented by both emerging memristor and traditional SRAM technologies. The proposed architecture achieves a promising efficiency for a variety of stencil applications and thus proves its applicability for scientific stencil computing.

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