Power optimization of system-level address buses based on software profiling

Fornaciari, William; Polentarutti,; Sciuto,; Silvano,

doi:10.1109/hsc.2000.843702

Cited by 7 publications

(14 citation statements)

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“…The authors in [5] combine T0 and bus-invert to achieve high energy efficiency. Applying transition signaling to T0 encoding to eliminate the redundant INC signal was proposed in [6]. Another extension of T0 encoding that eliminates the INC signal and achieves lower power dissipation was proposed in [7].…”

Section: Related Workmentioning

confidence: 99%

Cost-effective and low-power memory address bus encodings

Akl

Bayoumi

2008

2008 IEEE International Symposium on Circuits and Systems (ISCAS)

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this paper presents encoding methods that build on T0-encoding to achieve considerable reduction in memory address bus wires with small performance overhead, while reducing address bus switching activity. The known T0-encoding is combined with a variable cycle transmission technique that uses the T0's increment signal (INC) as an indicator of the number of cycles. Two of the proposed methods maintain the energy efficiency that is significantly reduced due to time-multiplexing.Benchmark experiments show that wire count of the instruction memory address bus can be reduced by around half at the price of 12.89% average performance penalty, while maintaining the low switching activity of the original T0-encoded bus.

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Section: Related Workmentioning

confidence: 99%

Cost-effective and low-power memory address bus encodings

Akl

Bayoumi

2008

2008 IEEE International Symposium on Circuits and Systems (ISCAS)

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“…Note that in address buses, the addresses are normally sequential except when the control flow instructions are encountered or exceptions occur [5]. A number of techniques for reducing the power consumption of address buses have been proposed (see, e.g., [4,[6][7][8][9][10]), which exploit the regularity of the buses. Data buses, in general, transfer highly uncorrelated data patterns and, therefore, may need more efforts for reducing the SA.…”

Section: Power Reduction In Busesmentioning

confidence: 99%

Sign Bit Reduction Encoding For Low Power Applications

Saneei

Afzali-Kusha

Navabi

2008

J Sign Process Syst Sign Image Video Technol

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In this paper, a low power technique, called SBR (Sign Bit Reduction), which reduces the energy consumption in multipliers as well as data buses is proposed. The technique reduces the number of sign bits in the data transfer as well as in the multiplication process. This feature enables us to use the encoding technique for both the transfer of the data and its multiplication at the destination without any need for an intermediate decoding step. Simple circuits are used as the SBR decoder and encoder. The efficacy of the technique is evaluated for both voice and random data. The results of applying the voice data to a 16-bit multiplier implemented with this scheme shows energy consumption up to 11.4% compared to those of a 2's complement implementation, while the number of required clock periods for the multiplication process is reduced up to 14.5%. The results of applying the SBR technique to a 30-tap FIR filter show up to 9.6% reduction in the energy consumption and up to 13.4% reduction in the required clock cycles. Finally, for voice data and random inputs, the use of the technique for a 16-bit data bus leads to an average energy consumption of up to 14.6%.

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“…As a result, bus layout becomes a critical issue in low power VLSI design. Previous work optimizes switching activity on individual wires [18] [5]. This might be inappropriate because switching activity does not necessarily reflect the power consumed by the bus.…”

Section: Introductionmentioning

confidence: 99%

Optimal partitioned fault-tolerant bus layout for reducing power in nanometer designs

Ruan

Naroska

Chen

2006

Proceedings of the 2006 International Symposium on Physical Design

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As technology scales down to nanometer dimensions, coupling capacitances between adjacent bus wires grow rapidly, and have a significant impact on power consumption and signal integrity of an integrated circuit. As buses are major components of a design, it is important to design fault-tolerant buses that dissipate less power and raise reliability without sacrificing performance. In this paper, we address the problem of using Hamming single error correcting code by optimizing both wire permutation and spacing. We propose an efficient polynomial time algorithm which applies graph theory for this optimization problem. Unlike previous studies [17], our approach can be applied to high bandwidth fault-tolerant buses to efficiently reduce the coupling capacitances by utilizing available space. For our experiments, we used instruction bus traces obtained from 12 SPEC2000 benchmark programs for evaluating energy reduction. The results show that our approach can save energy up to 43% for the best case, and 30% for the worst with 20 × dmin (dmin is the mininal permitted wire distance) additional width on RLC model. Besides, we also provided comprehensive comparisons in experimental result section for different fault-tolerant bus layout methods and error correction codes.

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Power optimization of system-level address buses based on software profiling

Cited by 7 publications

References 0 publications

Cost-effective and low-power memory address bus encodings

Cost-effective and low-power memory address bus encodings

Sign Bit Reduction Encoding For Low Power Applications

Optimal partitioned fault-tolerant bus layout for reducing power in nanometer designs

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