Power MOS transistors parameters at operation impacts

Emel’yanov, V. A.; Baranov, V.V.; Roubtsevich, I.I.; Anufriev, D.L.

doi:10.1109/isie.2005.1528959

Cited by 4 publications

(1 citation statement)

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“…In this work the task of physical and process simulation was solved to optimize power DMOS transistors with vertical structure and cell layout of HEXFET type, which includes up to several thousands of N-MOS transistor structures operating in parallel [3]. The solution of this task provides for design of chips having such impurity distribution in the areas of the semiconductor chip and cell layout sizes which secure optimal resistance values in the "open" state of the device, breakdown voltage, drain current, fast operation parameters and other characteristics including maximum good yield.…”

Section: Peculiarities Of Power Dmos Transistors Simulationmentioning

confidence: 99%

Simulation and Optimization of Power DMOS Transistors Parameters

Emel’yanov¹,

Baranov²,

Rubtsevich³

et al. 2006

2006 1st Electronic Systemintegration Technology Conference

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At present power DMOS transistors are regarded as one ofthe most prospective componentsfor many power-saving devices. When developing power DMOS transistors, which parameters are analogs ofIRL 640, "Transistor Factory " ofRPC "Integral " used the skills ofphysical and layout simulation and design of low-power LSI having N-channel MOS transistor structures. Based on this approach and using the developed original software, conducted was optimization ofparameters ofsolid-state structure ofpower DMOS transistors ofKP728E] type. In particular, minimized were the resistance values between the drain and source areas in the transistor "open " state, output andpass-by capacitances ofcell transistor structure when maintaining other parameters at the set level. Given are resistive and capacitance models ofa DMOS transistor. Resistance ofa conductive channel in an elementary cell ofa DMOS transistor was calculated as the sum ofcapacitances ofa solid-state structure, including herein the induced channel ofa horizontal N-MOS transistor, and the cell's capacitances are optimized taking into account SiO2 thickness in different parts ofthe structure.

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Section: Peculiarities Of Power Dmos Transistors Simulationmentioning

confidence: 99%

Simulation and Optimization of Power DMOS Transistors Parameters

Emel’yanov¹,

Baranov²,

Rubtsevich³

et al. 2006

2006 1st Electronic Systemintegration Technology Conference

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Simulation and parameters optimization of power DMOS Trench Field Effect Transistors

Baranov

Belous

Krechko

et al. 2010

3rd Electronics System Integration Technology Conference ESTC

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DMOS Trench Field Effect Transistors (TrenchFETs) have been taken as an object for electrical parameters optimization with the special developed software based on Excel table processor. Using this software the values of resistance between the source areas and the drain area of the open DMOS TrenchFET have been minimized as well as the values of the output and the internal capacitance of the cell transistor structure. The efficiency of the developed software is proved by the results of testing the manufactured series of DMOS TrenchFETs as their electrical parameters correspond to the best world known analogues.

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Optical electronic microdisplacement gage

Emel’yanov¹,

Baranov

Ilyin³

2007

2007 Mediterranean Conference on Control &Amp; Automation

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Developed were a model, a design and software of a precision device for measuring microdisplacement values, which can be used during automated control of geometrical parameters of various microobjects, and in particular in microelectronics I. INTRODUCTION During manufacture of integrated circuits and complicated solid-state devices (LSI, VLSI, microwave transistors, power microelectronics devices with good prospects etc.) having specific dimensions of layout elements of less than 1 µm, including herein 0.5 -0.13 µm, it is necessary to measure the period, width, thickness, position and quality of their peripherals. LSI elements of submicron dimensions, as well as those of nanoelectronics devices, are generated in layers of different materials (metals, dielectrics, semiconductors) which have 0.05 -1 µm thickness and significantly differ regarding optical and emission properties [1]. Specific feature of such threedimensional profile of a transition area of different shape, and the knowledge of geometrical structure of the area is necessary for high precision linear measurement at submicron level. At present for controlling geometrical parameters of such microobjects SEM methods are typical, but they are expensive and mostly used for failure analysis, and their use during routine inspection in LSI and VLSI technology is inefficient. A substantial problem in submicron technology is assurance and control of planarity and parallelism of surfaces of semiconductor wafers of big diameters, and these purposes SEM methods are also inapplicable [2, 3].

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Power MOS transistors parameters at operation impacts

Cited by 4 publications

References 0 publications

Simulation and Optimization of Power DMOS Transistors Parameters

Simulation and Optimization of Power DMOS Transistors Parameters

Simulation and parameters optimization of power DMOS Trench Field Effect Transistors

Optical electronic microdisplacement gage

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