Power-Loss and Design Space Analyses for Fully-Integrated Switched-Mode DC-DC Converters

Sun, Yin; Adrian, Victor; Chang, Joseph S.

doi:10.1109/iscas.2018.8351275

Cited by 4 publications

(6 citation statements)

References 9 publications

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“…The conduction loss and gate loss of the circuit can be dealt with similar to the method used in Ostman et al 36 and Sun et al 37 The conduction loss of

M_{1}

and

M_{3}

are as follows:

P_{c o n d, M_{1,3}} = \frac{2}{{normalμ}_{p} C_{o x} W false/ L false(V_{d d} - false| V_{T p} false| false)} false(D false) ((), Ī_{L}^{2} + \frac{I_{R p p}^{2}}{3}),

where

{normalμ}_{p}

is the mobility of holes.

C_{o x}

is the oxide capacitance per unit area and

V_{T p}

is PMOS threshold voltage.…”

Section: Design Proceduresmentioning

confidence: 99%

“…As mentioned before, GVD block consists of an inverter chain. The number of inverters

N

can be calculated as in Sun et al 37 If

k

is considered as the tapering factor between each stage, the power loss of GVD can be obtained as below:

P_{s w, G V D} = f C_{o x} W_{M_{1}} L_{M_{1}} V_{d d}^{2} true \sum_{m = 1}^{N} k^{m},

and if

k

is considered equal to 1/4 as in Alimadadi et al 38 and

N

is assumed to be large, thus

true \sum_{m = 1}^{N} k^{m}

in (3) converges to 1/3 and

α

is obtained equal to 4/3.…”

Section: Design Proceduresmentioning

confidence: 99%

“…The conduction loss and gate loss of the circuit can be dealt with similar to the method used in Ostman et al 36 and Sun et al 37 The conduction loss of M 1 and M 3 are as follows:…”

Section: Design Of M 1 M 2 and Mmentioning

confidence: 99%

See 2 more Smart Citations

A fully integrated soft switched high frequency resonant DC‐DC voltage regulator

Meshkat

Dehghani

Farzanehfard

2022

Circuit Theory & Apps

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Fully integrated 750-MHz resonant voltage regulator is presented. Providing soft switching conditions for the transistors has prevented degradation of the converter efficiency at this high switching frequency. High switching frequency has reduced volume of the passive on-chip components and thus increased the converter current density. Due to the limitations of the CMOS processes, control and gate drive circuits are designed to increase chip reliability. One of the major challenges of the fully integrated voltage regulators is the on-chip inductor realization. Based on the mathematical models for inductance and resistance of spiral on-chip inductor, the geometric dimensions of the employed inductor are optimally designed to have maximum quality factor and minimum chip area. The power switches are optimized to achieve maximum efficiency. All post layout parasitic elements of MOSFETs and metal routings including inductive effects are extracted using 3-D EM simulation and finite element method for 0.18-μm standard CMOS technology. Maximum output voltage ripple is 5.2% at maximum load current. Peak efficiency of the proposed on-chip power supply is 82% when input/output voltage is 1.8 V/1.48 V and load current is 120 mA. Maximum value of the efficiency enhancement factor is 42% for output input/voltage of 1.8 V/0.55 V. Current density of the proposed converter is 574 mA/mm 2 . In the worst case, the load step causes an overvoltage/undervoltage smaller than 15.56% at the output voltage. K E Y W O R D Sfully integrated voltage regulator (FIVR), soft switching, resonant DC-DC buck converter, high current density, on-chip inductor optimum design

show abstract

“…The conduction loss and gate loss of the circuit can be dealt with similar to the method used in Ostman et al 36 and Sun et al 37 The conduction loss of

M_{1}

and

M_{3}

are as follows:

P_{c o n d, M_{1,3}} = \frac{2}{{normalμ}_{p} C_{o x} W false/ L false(V_{d d} - false| V_{T p} false| false)} false(D false) ((), Ī_{L}^{2} + \frac{I_{R p p}^{2}}{3}),

where

{normalμ}_{p}

is the mobility of holes.

C_{o x}

is the oxide capacitance per unit area and

V_{T p}

is PMOS threshold voltage.…”

Section: Design Proceduresmentioning

confidence: 99%

“…As mentioned before, GVD block consists of an inverter chain. The number of inverters

N

can be calculated as in Sun et al 37 If

k

is considered as the tapering factor between each stage, the power loss of GVD can be obtained as below:

P_{s w, G V D} = f C_{o x} W_{M_{1}} L_{M_{1}} V_{d d}^{2} true \sum_{m = 1}^{N} k^{m},

and if

k

is considered equal to 1/4 as in Alimadadi et al 38 and

N

is assumed to be large, thus

true \sum_{m = 1}^{N} k^{m}

in (3) converges to 1/3 and

α

is obtained equal to 4/3.…”

Section: Design Proceduresmentioning

confidence: 99%

See 1 more Smart Citation

A fully integrated soft switched high frequency resonant DC‐DC voltage regulator

Meshkat

Dehghani

Farzanehfard

2022

Circuit Theory & Apps

View full text Add to dashboard Cite

show abstract

“…This compares very favorably over 1.1 for an on-chip metal-track planar spiral inductor. This can translate to an advantageous average power-efficiency improvement of >20%, when compared to a standard monolithically integrated CMOS DC-DC converter with an on-chip planar inductor [68].…”

Section: Inductors On Bonding Wiresmentioning

confidence: 99%

“…A large portion of this chapter is extracted from a paper submitted to the IEEE Transactions on Power Electronics [102] co-authored by the author of this thesis, and to a small part extracted from a provisional patent where the said author is a co-inventor.…”

Section: Switched-mode Dc-dc Converters With Bonding Wire Inductors 31 Introductionmentioning

confidence: 99%

Fully-integrated inductive switched-mode DC-DC converters

Sun¹

Self Cite

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An Integrated DC-DC Converter with Novel Asymmetrical Segmented Power-Stages for Sustained High Power-Efficiencies

Lee

Adrian

Chang

et al. 2022

2022 IEEE International Symposium on Circuits and Systems (ISCAS)

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Power-Loss and Design Space Analyses for Fully-Integrated Switched-Mode DC-DC Converters

Cited by 4 publications

References 9 publications

A fully integrated soft switched high frequency resonant DC‐DC voltage regulator

A fully integrated soft switched high frequency resonant DC‐DC voltage regulator

Fully-integrated inductive switched-mode DC-DC converters

An Integrated DC-DC Converter with Novel Asymmetrical Segmented Power-Stages for Sustained High Power-Efficiencies

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