Power integrity challenges of re-designing a mobile SoC with fully integrated voltage regulator to IoT applications

Shen, Yan

doi:10.1109/sapiw.2018.8401654

Cited by 3 publications

(2 citation statements)

References 2 publications

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“…which contain the losses of inductor and PCB, 3 increase for increasing switching frequencies. At f s = 50 MHz, the IVR achieves a maximum efficiency of 84.1 % at P out = 640 mW.…”

Section: Efficiency Measurements and Loss Breakdownmentioning

confidence: 99%

“…Cloud computing in data-centers, internet-of-things devices, as well as applications related to mobile communication, automotive, and artificial intelligence drive the needs for increased data processing capabilities of modern microprocessors, which, today, operate at clock frequencies up to 5 GHz [1] and have tens of cores in their more advanced versions [1]- [3]. Increased computational power of microprocessors has been achieved by reducing the transistors' gate widths to below 22 nm in recent technology nodes, leading to breakdown voltages of less than 1 V. However, the performance increase comes at the cost of increased power consumption, exceeding 150 W per device [4], and is accompanied by high supply currents reaching values close to 100 A considering a typical package voltage of 1.8 V [5].…”

Section: Introductionmentioning

confidence: 99%

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Electrical and Thermal Characterization of an Inductor-Based ANPC-Type Buck Converter in 14 nm CMOS Technology for Microprocessor Applications

Bezerra

Krismer

Kolar

et al. 2020

IEEE Open J. Power Electron.

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Integrated Voltage Regulators (IVRs) are attractive substitutes for conventional voltage regulators located on the motherboards, due to outstanding dynamic performances and superior power densities. IVRs operate with switching frequencies in the range of 100 MHz and are assembled in highly compact packages close to the microprocessor load. This paper presents a comprehensive characterization of a PCB-and inductorbased four-phase ANPC-type IVR that uses a Power Management IC (PMIC) implemented in a 14 nm CMOS technology node. The characterization is based on the results of electrical measurements, thermal inspections of the chip surface, and simulations, which enables the separation of the total losses into on-chip and off-chip loss components and the allocation of important loss components inside the chip. The investigated IVR achieves a maximum efficiency of 84.1 % at an output power of Pout = 640 mW and a switching frequency of fs = 50 MHz. The thermal measurements reveal that the maximum efficiency of the PMIC itself is between 88 % and 90 % at fs = 50 MHz and Pout ∈ [500 mW, 600 mW]; at Pout = 890 mW, a chip current density of 24.7 A/mm 2 is achieved. The findings in particular point out that the losses in the chip-internal interconnections, i.e., the conductors of the Power Distribution Network (PDN) and the twelve stacked metal layers below the PDN, have a substantial contribution to the total losses. Furthermore, the combination of Cadence post-layout simulations with impedance networks obtained from an appropriate software tool, e.g., FastHenry, is found to establish a suitable toolbox for estimating losses in IVRs.

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“…which contain the losses of inductor and PCB, 3 increase for increasing switching frequencies. At f s = 50 MHz, the IVR achieves a maximum efficiency of 84.1 % at P out = 640 mW.…”

Section: Efficiency Measurements and Loss Breakdownmentioning

confidence: 99%