Power Grid Physics and Implications for CAD

Pant, Sanjay; Blaauw, David; Chiprout, Eli

doi:10.1109/mdt.2007.78

Cited by 39 publications

(27 citation statements)

References 7 publications

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“…Since a fast charge delivery is limited by the large relaxation time of the on-chip power grid structure, initial current demands must be supplied by quiet decoupling capacitances in close proximity of the switching activity. It was confirmed through measurements [5][11] that on-chip decaps are efficient only when placed within a short physical distance of the switching components (standard cells, macroblocks, I/O drivers) and noise sources. Hence, to address power integrity and reduce the dynamic current spikes on the PDN, on-chip decaps must be placed in proximity of current-hungry blocks [12].…”

Section: Power Integrity and Emc-aware Design: An Overviewmentioning

confidence: 91%

“…Since fast current variations have a large harmonic content, a detrimental factor for EMC is the power rail noise or simultaneous switching noise (SSN) caused by the dynamic power and ground rail current fluctuations. In [5] it was demonstrated that SSN is originated mainly from package parasitic inductance, and with the increasing circuit frequencies and decreasing supply voltages, it is becoming more and more detrimental [6] [7]. Hence, adequate power rail noise suppression is a critical requirement for the successful design of today's microelectronic systems, and it necessitates among the other things the availability of low-impedance on-chip decoupling capacitors (i.e., decaps) to provide charge locally to the switching circuitry [8].…”

Section: Power Integrity and Emc-aware Design: An Overviewmentioning

confidence: 99%

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Understanding and modeling the impact of analog IPs on System-on-Chip's EMI

Forzan

Valente

Kumar

et al. 2012

International Symposium on Electromagnetic Compatibility - EMC EUROPE

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In modern digital ICs, the increasing demand for performance and throughput requires operating frequencies of hundreds of MHz, and in several cases exceeding the GHz range. Following the technology scaling trends, this request will continue to rise, thus increasing the electromagnetic interference (EMI) generated by electronic systems. The enforcement of strict governmental regulations and international standards, mainly (but not only) in the automotive domain, are driving new efforts towards design solutions, modeling, and analysis techniques for electromagnetic compatibility (EMC). In this paper we analyze the impact of analog IPs on the EMC behavior of complex System-on-Chip (SoC) designs, and we demonstrate that neglecting their contribution is a fallacy. The experimental results obtained on an industrial automotive microcontroller validate the effectiveness of the proposed approach.

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Section: Power Integrity and Emc-aware Design: An Overviewmentioning

confidence: 91%

Section: Power Integrity and Emc-aware Design: An Overviewmentioning

confidence: 99%

Understanding and modeling the impact of analog IPs on System-on-Chip's EMI

Forzan

Valente

Kumar

et al. 2012

International Symposium on Electromagnetic Compatibility - EMC EUROPE

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“…As a consequence, the impedance of the power and ground network increases with the resonance frequency which further augments the supply noise. Authors in [12] have studied the impact of package inductance at different frequencies to estimate the amount of supply noise generated. They have concluded that there are high and mid/low frequency supply noises generated.…”

Section: Impact Of Resonance Frequencymentioning

confidence: 99%

A study of path delay variations in the presence of uncorrelated power and ground supply noise

Todri

Bosio

Dilillo

et al. 2011

14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems

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As technology scales down, the effects of power supply noise and ground bounce are becoming significantly important. In the existing literature, it has been shown that excessive power supply noise can affect the path delay, while ground bounce is either neglected or assumed similar to power supply noise. In this work, we present a detailed study of combined and uncorrelated power supply noise and ground bounce and their impact on the path delay. Our analyses show that different combination of power supply noise and ground bounce can lead to either delay speed-up or slow-down. Furthermore, our study shows the degrading influence of supply noise resonance on the path delay. We perform HSPICE simulations for path delay analysis on various technology nodes i.e. 130nm, 90nm, 65nm and 45nm

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“…Moreover, path delays in a 3D-IC already experience variations due to the physical and electrical conditions [3]- [6] such as nonuniform switching, supply noise (such as IR-drop), TSVto-TSV coupling and coupling through the lossy substrate. These conditions tend to affect path delay and may result in incremental signal delay through the path or even cause artificial speed-up or slow-down due to different voltage potentials between driver and receiver gates.…”

Section: Introductionmentioning

confidence: 99%

Timing-aware ATPG for critical paths with multiple TSVs

Metzler

Todri‐Sanial

Bosio

et al. 2014

17th International Symposium on Design and Diagnostics of Electronic Circuits &Amp; Systems

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International audienceThrough-Silicon-Vias (TSVs) are the key enablers of 3D integration technology. Therefore, the reliability of 3D-ICs rely on the quality of TSV testing. TSVs are prone to defects that may introduce small delay variations that can cause quality and reliability issues. Moreover, physical and electrical conditions, such as TSV dimensions, coupling and IR-drop, may affect path delay variations and consequently affect the detectability of small delay faults (SDF) induced by defective TSVs. In this work, we study the test quality and pattern effectiveness for SDF induced by TSVs. We quantity test quality using statistical delay quality level (SDQL) metric and test patterns are generated with commercial ATPG tools

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Power Grid Physics and Implications for CAD

Cited by 39 publications

References 7 publications

Understanding and modeling the impact of analog IPs on System-on-Chip's EMI

Understanding and modeling the impact of analog IPs on System-on-Chip's EMI

A study of path delay variations in the presence of uncorrelated power and ground supply noise

Timing-aware ATPG for critical paths with multiple TSVs

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