A study of path delay variations in the presence of uncorrelated power and ground supply noise

Todri, A.; Bosio, Alberto; Dilillo, Luigi; Girard, Patrick; Pravossoudovitch, S.; Virazel, Arnaud

doi:10.1109/ddecs.2011.5783078

Cited by 4 publications

(1 citation statement)

References 14 publications

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“…Analysis shows that power supply noise and ground bounce can considerably affect circuit's performance [1]. Furthermore, simulations show that delay can have a speed-up/slow-down effect depending on the noise conditions on the neighboring gates and/or the crosstalk between gates as shown, respectively, by [2] and [3]. We consider the uncorrelated behavior of power supply noise and ground bounce (independent noise peaks and frequencies) in order to represent them as realistically as they would occur in an actual design.…”

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confidence: 99%

Uncorrelated Power Supply Noise and Ground Bounce Consideration for Test Pattern Generation

Todri

Bosio

Dilillo

et al. 2013

IEEE Trans. VLSI Syst.

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Power supply noise and ground bounce can cause considerable path delay variations. Capturing the worst case power supply noise at a gate level is not a sufficient indicator for measuring the worst case path delay. Furthermore, path delay variations depend on multiple parameters such as input stimuli, cell placement, switching frequency, and available decoupling capacitors. All these variables obscure the rapport between supply noise and path delay and make the selection of stimuli for worst case path delay a difficult task during test pattern generation. In this paper, we utilize power supply noise and ground bounce distribution along with physical design data to generate test patterns for capturing worst case path delay. We propose accurate close-form mathematical models for capturing the effect of power supply noise and ground bounce on path delay. These models are based on modified nodal analysis formulation of power and ground networks, where current waveforms are obtained from levelized simulation and cell library characterization. The proposed test pattern generation flow is a simulatedannealing-based iterative process, which utilizes mathematical models for capturing the impact of supply noise on path delay for a given input pattern. We perform experiments on ITC'99 benchmarks and show that path delay variation can be considerable if test patterns are not properly selected.

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confidence: 99%