Power gating in wireless sensor networks

Panić, Goran; Stamenković, Zoran; Kraemer, Rolf

doi:10.1109/iswpc.2008.4556258

Cited by 16 publications

(10 citation statements)

References 19 publications

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“…The results are shown for two different t a (0.1% and 1%) and γ (5% and 10%) values. Since power gated circuits tend to have long standby times, t a values were kept ≤ 1% [14]. Column Energy (PG + FBB) shows the total leakage energy by using PG + FBB technique.…”

Section: Experimental Setup and Resultsmentioning

confidence: 99%

Improving efficiency of power gated circuits through concurrent optimization of power switch size and forward body biasing

Sathanur

Ashouei

Huisken

2010

2010 IEEE International Conference on Integrated Circuit Design and Technology

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Power gating (PG) has emerged as an effective technique to reduce standby leakage power in portable devices where battery life time is vital. However, it comes at the cost of timing overhead which is a problem for most of the applications where real-time constraints exist. Designing efficient power gated circuits is very challenging problem due to contrasting requirements in active mode (low timing overhead implying larger power switch size) and standby mode (low standby leakage power implying smaller power switch size). In this work, we show that applying Forward Body Biasing (FBB) to the logic gates in conjunction with power gating (PG + FBB) will provide us with an additional degree of freedom which can be utilized to improve the efficiency of the power gated circuit. We propose an optimization algorithm to find the optimum power switch size and FBB value such that total leakage energy of the design (active + standby) in minimized. Results show that our PG + FBB technique on an average improves the leakage energy savings by 2X-5X as compared to using only power gating. With PG + FBB technique, one can also design a zero delay penalty power gated circuit which is not possible if only power gating is used.

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Section: Experimental Setup and Resultsmentioning

confidence: 99%

Improving efficiency of power gated circuits through concurrent optimization of power switch size and forward body biasing

Sathanur

Ashouei

Huisken

2010

2010 IEEE International Conference on Integrated Circuit Design and Technology

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“…The ratio P d / P s is technology dependent and is proportional to the MOS transistor channel properties. Similarly as in [18] 1 , taking the corresponding P d / P s for three different CMOS technologies, we have calculated the impact of energy loss in respect to the total energy consumption in terms of a DC factor. The obtained results are presented in Fig.…”

Section: Duty Cyclingmentioning

confidence: 99%

“…In order to extend the lifetime of SN, a wide variety of techniques for minimizing SN's energy consumption have been proposed in literature [4], [5], [6]. Some of them deal with saving energy at MAC (Media Access Control) level [7], [8], [9], others at routing protocols [10], [11], [12], third with dissemination data aggregations or fusion [13], [14], fourth with involving novel architectures that utilize the optimized radio and digital parts [15], [16], [17], fifth employ on-chip power gating in order to reduce the static power loss [18], [19]. To address the problem of power saving within a SN, two promising approaches based on dynamic voltage scaling [20], [21] and power gating [22], [23] are used.…”

Section: Introductionmentioning

confidence: 99%

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Wireless sensor node with low-power sensing

et al. 2014

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Wireless sensor network consists of a large number of simple sensor nodes that collect information from external environment with sensors, then process the information, and communicate with other neighboring nodes in the network. Usually, sensor nodes operate with exhaustible batteries unattended. Since manual replacement or recharging of the batteries is not an easy, desirable or always possible task, the power consumption becomes a very important issue in the development of these networks. The total power consumption of a node is a result of all steps of the operation: sensing, data processing and radio transmission. In most published papers in literature it is assumed that the sensing subsystem consumes significantly less energy than a radio block. However, this assumption does not apply in numerous applications, especially in the case when power consumption of the sensing activity is comparably bigger than that of a radio. In that context, in this work we focus on the impact of the sensing hardware on the total power consumption of a sensor node. Firstly, we describe the structure of the sensor node architecture, identify its key energy consumption sources, and introduce an energy model for the sensing subsystem as a building block of a node. Secondly, with the aim to reduce energy consumption we investigate joint effectiveness of two common power-saving techniques in a specific sensor node: duty-cycling and power-gating. Duty-cycling is effective at the system level. It is used for switching a node between active and sleep mode (with the dutycycle factor of 1%, the reduction of in dynamic energy consumption is achieved). Power-gating is used at the circuit level with the goal to decrease the power loss due to the leakage current (in our design, the reduction of dynamic and static energy consumption of off-chip sensor elements as constituents of sensing hardware within a node of is achieved). Compared to a sensor node architecture in which both energy saving techniques are omitted, the conducted MATLAB simulation results suggest that in total, thanks to involving duty-cycling and power-gating techniques, a three order of magnitude reduction for sensing activities in energy consumption can be achieved.

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“…For certain specific low activity battery-operated embedded systems used in applications, e.g., environment monitoring sensors, biomedical implants, the sleep mode power, though having a low value, adds up to an energy figure that represents a significant fraction from the total energy consumed by the chip [4], [5]. For this reason new ways to further reduce the leakage power while mitigating the area and delay penalty are needed.…”

Section: Introductionmentioning

confidence: 99%

Advanced NEMS-based power management for 3D Stacked Integrated Circuits

Enachescu

Voicu

Cotofana

2010

2010 International Conference on Energy Aware Computing

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Abstract-In this paper we introduce a novel power management architecture for 3D Through Silicon Vias based integration technology. Our approach relies on the synergy of two new technological developments as follows: (i) we utilize a NanoElectroMechanical (NEM) device, the Suspended Gate FET (SG-FET), as sleep transistor; and (ii) we make use of the 3D potential by placing the sleep transistor (the entire power management infrastructure) on a dedicated tier of the 3D stacked Integrated Circuit. Due to the extreme low leakage current of the SG-FET our proposal results in 2 orders of magnitude static power reduction, when compared with equivalent counterparts based on traditional CMOS devices. The SG-FET power switch requires about 4x more area when compared to bulk CMOS, however, due to the 3D integration which allows for heterogeneous dies to be stacked, the power gating devices can be placed to a low cost dedicated layer, which also results in a substantial IR-drop reduction with minimum impact on leakage.

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Power gating in wireless sensor networks

Cited by 16 publications

References 19 publications

Improving efficiency of power gated circuits through concurrent optimization of power switch size and forward body biasing

Improving efficiency of power gated circuits through concurrent optimization of power switch size and forward body biasing

Wireless sensor node with low-power sensing

Advanced NEMS-based power management for 3D Stacked Integrated Circuits

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