Power estimation for field programmable gate arrays

One of the mq'or drawbacks of field programmable gate arrays is their poor energy eficienq. This paper focuses on the routing phase of FPGA design and attempts to optimize dynamic power consumption in FPGA interconnect. Power optimization is performed with small side effects on circuit performance and area. Our enhancements to the VPR Timing Driven algorithm reduced the FPGA routing power by about IO% with negligible loss in circuitperformance.

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Power Testing of an FPGA based System Using Modelsim Code Coverage capability

Arshak

Jafer

Ibala

2007

2007 IEEE Design and Diagnostics of Electronic Circuits and Systems

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Abstract-Field programmable gate arrays (FPGAs) play many important roles, ranging from small glue logic replacement to System-on-Chip designs. Nevertheless, FPGA vendors can not accurately specify the energy consumption information of their products on the device data sheets because the energy consumption of FPGAs is strongly dependent on target circuit including resource utilization, logic partitioning, mapping, placement and route. While major CAD tools have started to report average power consumption under given transition activities, energy optimal FPGA design demands more detailed energy estimation.The target design is telemetry system used for health monitoring applications. The FPGA is acting as the controller unit of both transmitter and receiver. Transmitter side is reading data from interfaced sensors. Verilog-HDL has been used to implement the required functions of the FPGA. In this paper, the power performance of the FPGA based design will be investigated using XILINX Xpower tool. Modelsim Code coverage feature has been incorporated to make sure that the test-bench cover all the nets branch statement of the design and create the most accurate Value Change Dump (VCD) file for the power consumption estimation.

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Power estimation for field programmable gate arrays

Cited by 11 publications

References 45 publications

A New Behavioural Power Modelling Approach for FPGA based Custom Cores

A New Behavioural Power Modelling Approach for FPGA based Custom Cores

Reducing power consumption in FPGA routing

Power Testing of an FPGA based System Using Modelsim Code Coverage capability

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