2022
DOI: 10.1109/jiot.2022.3172843
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Power-Efficient Implementation of Ternary Neural Networks in Edge Devices

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Cited by 3 publications
(2 citation statements)
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“…In its final version, power optimized AI networks running on FPGA should take over this task. In this scope, a framework to train, optimize and implement such algorithms has been developed [13]. Furthermore, a self-pose estimation system running on the NVIDIA Jetson Nano is under development.…”
Section: Communication Systems Facilitating Bvlos Drone Servicesmentioning
confidence: 99%
“…In its final version, power optimized AI networks running on FPGA should take over this task. In this scope, a framework to train, optimize and implement such algorithms has been developed [13]. Furthermore, a self-pose estimation system running on the NVIDIA Jetson Nano is under development.…”
Section: Communication Systems Facilitating Bvlos Drone Servicesmentioning
confidence: 99%
“…This approach is particularly beneficial when hardware parallelization of the algorithms is possible, as with most of the Artificial Neural Networks (ANNs) topologies. For this reason, the first efforts have been focused into the creation a framework to train, optimize, and implement ANNs on FPGAs, as presented in [16]. The goal of this framework is to provide highly certified and sustainable solution for resource and energy-constrained devices.…”
Section: Hardware Co-design Power Optimizationmentioning
confidence: 99%