Power-efficient focal-plane image representation for extraction of enriched Viola-Jones features

Abstract

This paper describes the use of a reconfigurable focal-plane processing array in order to achieve an image representation which dramatically reduces the computational load of the Viola-Jones object detection framework. Additionally, such representation provides richer information than the simple sum of pixels within rectangular regions originally defined in this framework. As a result, more elaborated features could be devised to speed up the execution of the subsequent attentional cascade, boosting thus the performance of the whole algorithm. The proposed circuitry has been successfully implemented in a CMOS prototype smart imager. Experimental results are given, demonstrating the suitability of the approach presented to efficiently deliver enriched Viola-Jones features.

AMBA bus hardware accelerator IP for Viola–Jones face detection

“…Other implementations use hardware approach (application‐specific integrated circuit (ASIC) or field‐programmable gate array (FPGA) to accelerate (completely or partially) the face detection algorithm [6]. Theocharides et al [7] proposed an ASIC‐based architecture that heavily exploits parallelism of the AdaBoost face recognition technique by parallelising accesses of image data.…”