Power Efficient and High Speed Multiplier Bbased on Ancient Mathematics: A Review

G, Praveen Kumar Y; Karivappa, B S; Patil, Basavaraj H; Naik, Anil Kumar; Kumar, P. Sai; Kurian, M Z

doi:10.1109/icesc48915.2020.9155709

Cited by 6 publications

(2 citation statements)

References 7 publications

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“…Same year 2016, Kapil Ram Gavali and Poonam Kadam has proposed a unique structural design for the accomplishment of signed multiplication. 11×8 multiplier was designed and implemented by using the Xilinx ISE design suite [22][23]. In the year 2017, VijayaLakshmi Bandi have proposed Vedic multiplier, which is designed using modified full adders which consume fewer LUT's and less delay in comparisons of existing multiplier [22,23].…”

Section: Literature Reviewmentioning

confidence: 99%

Analysis of Multiplication Based on Vedic Mathematics

Lakshmi

Kishore

Kumar

2022

Advances in Transdisciplinary Engineering

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The usual segmentation methods were addressed here: edge detection, clustering, and region growth. The problem with segmentation is that no one approach is suited for a certain type of picture, nor are all techniques applicable to all images. The importance of multiplication is rising according to the technology process. It is one of the major applications which is used in various domains such as business and digital signal process etc. The way of general multiplication is much more time taking process. So, mainly as to remove this time delay in this paper the concept of Vedic mathematics is introduced. This paper introduced about Indian ancient Vedic mathematics is involved to clear those problems. Sixteen sutras among the Vedic mathematics the one sutra that is widely used and implemented is “URDHVA-TIRYAGBHYAM” is proposed. The multiplication process of two 4 bit and two 3 bit and also two 2-bit multiplications are gone through this paper. This process ultimately leads to the consumption of less time and faster implementation. But, with respect to the order of multiplication, the complexity will also increase. When compared to other multipliers it takes less area.

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Section: Literature Reviewmentioning

confidence: 99%

Analysis of Multiplication Based on Vedic Mathematics

Lakshmi

Kishore

Kumar

2022

Advances in Transdisciplinary Engineering

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“…Logic gates with reversible con gurations, such as reversible logic designs, are ideal for reducing circuit power consumption. structures[Kumar et al (2020)]. Theuse of an 8-cycle Vedic multiplier and the transmission of a save snake is suggested for a 16-digit MAC unit.…”

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confidence: 99%

Design of a Novel Arithmetic Architecture Using Hybrid Vedic Sutras in Digital Signal Processing Applications

RAMAMOORTHY,

PERIASAMY

2023

Preprint

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Digital signal processing (DSP) is a vast and active field of research. High throughput is required for most wireless communication systems. The Fast Fourier Transform (FFT), which lies at the heart of most modulators, is a major stumbling block to communication.The intrinsic floating-point multiplier units located within the butterfly units of every FFT execute these calculations. The performance of FFT in terms of throughput is limited by multiplication. As a result, Multiplier topologies with reduced truncation errors are needed for high-speed, low-power systems. This paper presents high-performance FFT units for DSP processor cores based on hybrid Vedic multiplier units. The Vedic multiplier that has been presented is based on the Vedic multiplication sutras. In the decimal number system, these sutras have historically been employed to multiply two numbers. In this study, a hybrid Vedic multiplier based on Indian Vedic mathematics' Urdhva-Tiryagbhyam and Nikhilam navatascaramam sutra is suggested. An efficient multiplier is the fundamental goal of this study, which aims to minimize the size and delay path of a multiplier while enhancing the performance of the processor. Verilog HDL was used to implement the complete design. Xilinx ISE Design Suite 14.5, which is used for synthesis and simulations, was used. It is matched to previously reported Vedic multiplier designs in terms of speed and area consumed. It features a speedier development process and a lower computation complexity than the traditional multiplier.

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Comparative analysis of Vedic multiplier using Vedic sutras with existing multipliers in biomedical application

Karthi Kumar,

Vimal

2024

Measurement: Sensors

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Power Efficient and High Speed Multiplier Bbased on Ancient Mathematics: A Review

Cited by 6 publications

References 7 publications

Analysis of Multiplication Based on Vedic Mathematics

Analysis of Multiplication Based on Vedic Mathematics

Design of a Novel Arithmetic Architecture Using Hybrid Vedic Sutras in Digital Signal Processing Applications

Comparative analysis of Vedic multiplier using Vedic sutras with existing multipliers in biomedical application

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