Design of a Novel Arithmetic Architecture Using Hybrid Vedic Sutras in Digital Signal Processing Applications

Abstract

Digital signal processing (DSP) is a vast and active field of research. High throughput is required for most wireless communication systems. The Fast Fourier Transform (FFT), which lies at the heart of most modulators, is a major stumbling block to communication.The intrinsic floating-point multiplier units located within the butterfly units of every FFT execute these calculations. The performance of FFT in terms of throughput is limited by multiplication. As a result, Multiplier topologies with reduced truncation errors are needed for high-speed, low-power systems. This paper presents high-performance FFT units for DSP processor cores based on hybrid Vedic multiplier units. The Vedic multiplier that has been presented is based on the Vedic multiplication sutras. In the decimal number system, these sutras have historically been employed to multiply two numbers. In this study, a hybrid Vedic multiplier based on Indian Vedic mathematics' Urdhva-Tiryagbhyam and Nikhilam navatascaramam sutra is suggested. An efficient multiplier is the fundamental goal of this study, which aims to minimize the size and delay path of a multiplier while enhancing the performance of the processor. Verilog HDL was used to implement the complete design. Xilinx ISE Design Suite 14.5, which is used for synthesis and simulations, was used. It is matched to previously reported Vedic multiplier designs in terms of speed and area consumed. It features a speedier development process and a lower computation complexity than the traditional multiplier.