Power efficient all-digital delta-sigma TDC with differential gated delay line time integrator

Parekh, Parth; Yuan, Fei

doi:10.1109/icam.2017.8242131

Cited by 7 publications

(7 citation statements)

References 12 publications

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“…In systems such as bi-directional gated delay line time integrators, the time variable to be integrated is the gating signal of the gated delay line [10]. Both the polarity and absolute value of the gating signal are needed as the former sets the direction of signal propagation while the latter determines the distance over which the signal propagates in the delay line.…”

Section: Absolute Value Of Time Variablesmentioning

confidence: 99%

“…Fig. 3 shows portion of a first-order ΔΣ TDCs utilising a bidirectional gated delay line time integrator [10]. The difference between the analogue input to be digitised and the output of the Digital-to-Analog Converter in the feedback loop, denoted by T err , is fed to the absolute-value block |T err | where both the absolute value of T err and the sign of T err are generated.…”

Section: Absolute Value Of Time Variablesmentioning

confidence: 99%

“…Fig. 18a shows the schematic of the time subtracter of a 1-bit ΔΣ TDC [10]. If D out = 1, indicating the output of the time integrator exceeds the threshold of the quantiser, T FB will be subtracted from T in in order to lower T err subsequently the output of the time integrator.…”

Section: Time Addition Using a Udgdlmentioning

confidence: 99%

“…The bi-directional gated delay cell shown in Fig. 22 consists of two gated delay cells and is capable of propagating signals in both directions, depending upon the polarity of T in to be integrated [10,21]. In order for the time integrator to have output range −Mτ ≤ T out ≤ Mτ, where τ is the per-stage delay, a total of 2M + 1 identical gated delay stages are needed.…”

Section: Time Integrator Using Bi-directional Gated Delay Linementioning

confidence: 99%

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Design techniques of all‐digital arithmetic units for time‐mode signal processing

Yuan

2018

IET Circuits, Devices & Systems

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This study provides a comprehensive treatment of the design techniques of all-digital arithmetic units for time-mode signal processing. The arithmetic units investigated include time polarity detectors, time absolute-value generators, time adders, time baluns, time amplifiers, time quantisers, time registers, and time integrators. The principle, circuit implementation, constraints and limitations of these units are investigated in detail. An emphasis is given to time adders and time integrators. An in-depth study of time adders constructed from switched delay units, dual discharge paths, and unidirectional gated delay lines is provided. It is followed with the presentation of three time registered evolved from these time adders. Three time integrators developed from the preceding time adders and time registers are studied and their characteristics are compared. Finally, the design of a first-order ΔΣ time-to-digital converter utilising these arithmetic units is presented.

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Section: Absolute Value Of Time Variablesmentioning

confidence: 99%

Section: Absolute Value Of Time Variablesmentioning

confidence: 99%

Section: Time Addition Using a Udgdlmentioning

confidence: 99%

Section: Time Integrator Using Bi-directional Gated Delay Linementioning

confidence: 99%

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Design techniques of all‐digital arithmetic units for time‐mode signal processing

Yuan

2018

IET Circuits, Devices & Systems

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“…As time addition is achieved by gating the discharging paths of a pre-charged capacitor and the discharging current varies with the voltage of the capacitor due to the change of the mode of the operation of current-discharging transistors and their finite output resistance, the time integrator is inherently non-linear. In [14], an all-digital ΔΣ TDC with dual bi-directional gated delay line (BDGDL) time integrators and two digital-to-time converters (DTCs) was proposed. Not only mismatches between the BDGDLs and those between DTCs introduce errors, the need for two BDGDLs and two DTCs also increases power consumption.…”

Section: Introductionmentioning

confidence: 99%

Time‐based all‐digital time‐to‐digital converter with pre‐skewed bi‐directional gated delay line time integrator

Yuan

Parekh

2019

IET Circuits, Devices & Systems

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An all-digital first-order single-bit ΔΣ time-to-digital converter (TDC) with a pre-skewed bi-directional gated delay line (PS-BDGDL) time integrator with built-in self-quantisation is presented in this study. Pre-skewing is utilised to lower the perstage delay of the BDGDL and minimise the skew errors of BDGDLs. The impact of the strength and timing of pre-skewed is analysed. The reduction of skew errors obtained from pre-skewing is also analysed. A design methodology combating the impact of process uncertainty on the TDC is developed. The TDC is designed in an IBM 130 nm 1.2 V CMOS technology and analysed using Spectre from Cadence Design Systems with BSIM4 device models. Simulation results show that the impact of process spread on the performance of the TDC can be minimised by adjusting the delay of the key delay blocks and the perstage delay of the gated delay stages. The figure-of-merit of the TDC outperforms reported TDCs alike.

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All-Digital Delta-Sigma TDC with Differential Multipath Pre-Skewed Gated Delay Line Time Integrator

Yuan

Parekh

2018

2018 IEEE 3rd International Conference on Integrated Circuits and Microsystems (ICICM)

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Power efficient all-digital delta-sigma TDC with differential gated delay line time integrator

Cited by 7 publications

References 12 publications

Design techniques of all‐digital arithmetic units for time‐mode signal processing

Design techniques of all‐digital arithmetic units for time‐mode signal processing

Time‐based all‐digital time‐to‐digital converter with pre‐skewed bi‐directional gated delay line time integrator

All-Digital Delta-Sigma TDC with Differential Multipath Pre-Skewed Gated Delay Line Time Integrator

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