All-Digital Delta-Sigma TDC with Differential Multipath Pre-Skewed Gated Delay Line Time Integrator

Yuan, Fei; Parekh, Parth

doi:10.1109/icam.2018.8596506

Cited by 4 publications

(1 citation statement)

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“…In [18], a pre‐skewed uni‐directional gated delay line time register was proposed to lower skew errors. This paper extends our early work in [19] and presents an all‐digital

normalΔ false\sum

TDCs with a PS‐BDGDL time integrator with built‐in self‐quantisation. The remainder of the paper is organised as follows: Section 2 introduces a PS‐BDGDL time integrator.…”

Section: Introductionsupporting

confidence: 58%

Time‐based all‐digital time‐to‐digital converter with pre‐skewed bi‐directional gated delay line time integrator

Yuan

Parekh

2019

IET Circuits, Devices & Systems

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An all-digital first-order single-bit ΔΣ time-to-digital converter (TDC) with a pre-skewed bi-directional gated delay line (PS-BDGDL) time integrator with built-in self-quantisation is presented in this study. Pre-skewing is utilised to lower the perstage delay of the BDGDL and minimise the skew errors of BDGDLs. The impact of the strength and timing of pre-skewed is analysed. The reduction of skew errors obtained from pre-skewing is also analysed. A design methodology combating the impact of process uncertainty on the TDC is developed. The TDC is designed in an IBM 130 nm 1.2 V CMOS technology and analysed using Spectre from Cadence Design Systems with BSIM4 device models. Simulation results show that the impact of process spread on the performance of the TDC can be minimised by adjusting the delay of the key delay blocks and the perstage delay of the gated delay stages. The figure-of-merit of the TDC outperforms reported TDCs alike.

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“…In [18], a pre‐skewed uni‐directional gated delay line time register was proposed to lower skew errors. This paper extends our early work in [19] and presents an all‐digital

normalΔ false\sum

TDCs with a PS‐BDGDL time integrator with built‐in self‐quantisation. The remainder of the paper is organised as follows: Section 2 introduces a PS‐BDGDL time integrator.…”

Section: Introductionsupporting

confidence: 58%