Power driven chaining of flip-flops in scan architectures

Bonhomme, Yannick; Girard, Patrick; Landrault, C.; Pravossoudovitch, S.

doi:10.1109/test.2002.1041833

Cited by 85 publications

(92 citation statements)

References 20 publications

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“…However, the careful observation of experimental results of [12] and [8] indicates that for most of the benchmarks the work by Bonhomme et al [12] is performing better for shift cycle peak power. Table 4 show that the proposed work is able to reduce the peak power up to 48.29% in comparison to the industrial solution and 28.51% in comparison to [12] for circuit s13207. For circuit s35932 the proposed work and the work by [12] are able to reduce the power singificantly due to the favourable combination of smaller number of pattern set and large scan chain.…”

Section: Resultsmentioning

confidence: 98%

“…Specification of benchmark circuits and experimental results are provided in Table 3 and Table 4 respectively. To show the effectiveness of the proposed work we have compared the experimental results with the scan order provided by industrial tool and with the average power scan order proposed by Bonhomme et al [12]. We have chosen [12] as the suitable reference to compare our results reason being this is the only work on scan cell reordering for minimization of average and peak power.…”

Section: Resultsmentioning

confidence: 99%

“…To show the effectiveness of the proposed work we have compared the experimental results with the scan order provided by industrial tool and with the average power scan order proposed by Bonhomme et al [12]. We have chosen [12] as the suitable reference to compare our results reason being this is the only work on scan cell reordering for minimization of average and peak power. Another nearest candidate would be the methodology by Badereddine et al [8].…”

Section: Resultsmentioning

confidence: 99%

“…Another nearest candidate would be the methodology by Badereddine et al [8]. However, the careful observation of experimental results of [12] and [8] indicates that for most of the benchmarks the work by Bonhomme et al [12] is performing better for shift cycle peak power. Table 4 show that the proposed work is able to reduce the peak power up to 48.29% in comparison to the industrial solution and 28.51% in comparison to [12] for circuit s13207.…”

Section: Resultsmentioning

confidence: 99%

“…An technique based on scan partition called as adaptive scan architecture was proposed by [16]. Another work on average power reduction is done by Girard et al [14] and Bonhomme et al [12]. The basic idea behind these works is to reorder the scan cells.…”

Section: Previous Workmentioning

confidence: 99%

See 4 more Smart Citations

Graph theoretic approach for scan cell reordering to minimize peak shift power

Tudu

Larsson

Singh

et al. 2010

Proceedings of the 20th Symposium on Great Lakes Symposium on VLSI

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Scan circuit testing generally causes excessive switching activity compared to normal circuit operation. This excessive switching activity causes high peak and average power consumption. Higher peak power causes, supply voltage droop and excessive heat dissipation. This paper proposes a scan cell reordering methodology to minimize the peak power consumption during scan shift operation. The proposed methodology first formulate the problem as graph theoretic problem then solve it by a linear time heuristic. The experimental results show that the methodology is able to reduce up to 48% of peak power in compared to the solution provided by industrial tool.

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Section: Resultsmentioning

confidence: 98%

Section: Resultsmentioning

confidence: 99%

Section: Resultsmentioning

confidence: 99%

Section: Resultsmentioning

confidence: 99%

Section: Previous Workmentioning

confidence: 99%

See 3 more Smart Citations

Graph theoretic approach for scan cell reordering to minimize peak shift power

Tudu

Larsson

Singh

et al. 2010

Proceedings of the 20th Symposium on Great Lakes Symposium on VLSI

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Deterministic Test Vector Compression / Decompression Using an Embedded Processor

Bellos

Nikolos

2005

Dependable Computing - EDCC 5

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Abstract.Test data compression and on-chip decompression using an embedded processor has already been proposed for test data volume and test time reduction as well as for use of slower testers without decreasing test quality. On the other hand, scan cell reordering methods have been proposed to overcome the problem of high average power dissipation during scan based external testing. In this paper we propose a scan cell ordering based test vector compression method, which reduces test data volume up to 87.3%. The decompression of the test data is based on the use of an embedded processor.

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Scan Cell Reordering for Peak Power Reduction during Scan Test Cycles

Badereddine

Girard

Pravossoudovitch

et al.

Vlsi-Soc: From Systems to Silicon

Self Cite

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Scan technology increases the switching activity well beyond that of the functional operation of an IC. In this paper, we first discuss the issues of excessive peak power during scan testing and highlight the importance of reducing peak power particularly during the test cycle (i.e. between launch and capture) so as to avoid noise phenomena such as IR-drop or Ground Bounce. Next, we propose a scan cell reordering solution to minimize peak power during all test cycles of a scan testing process. The problem of scan cell reordering is formulated as a constrained global optimization problem and is solved by using a simulated annealing algorithm. Experimental evidence and practical implications of the proposed solution are given at the end of the paper. For ISCAS'89 and ITC'99 benchmark circuits, this approach reduces peak power during TC up to 51% compared to an ordering provided by an industrial synthesis tool. Fault coverage and test time are left unchanged by the proposed solution.

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Power driven chaining of flip-flops in scan architectures

Cited by 85 publications

References 20 publications

Graph theoretic approach for scan cell reordering to minimize peak shift power

Graph theoretic approach for scan cell reordering to minimize peak shift power

Deterministic Test Vector Compression / Decompression Using an Embedded Processor

Scan Cell Reordering for Peak Power Reduction during Scan Test Cycles

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