Power conversion schemes in nanometer CMOS mixed-signal SoCs

Abstract

An overview of various schemes for realizing a large number of on-chip power supply domains in mixed-signal System-on-Chip (SoCs) implemented in nanometer CMOS technologies are presented. This includes two-step power conversion schemes that employ a separate Power Management Integrated Circuit (PMIC) to generate few shared highlyefficient power supplies, followed by secondary fully-integrated power converters to generate multiple on-chip power supplies inside the SoC. Three alternatives for implementing the secondary power converters will be discussed, which includes linear regulators as well as fully-integrated inductor-based and capacitor-based high-frequency switching regulators. An overview of single-step power conversion schemes based on Single-Inductor-Multiple-Output (SIMO) switching power converters will also be presented. The advantages and limitations of these various schemes in terms of power conversion efficiency and dynamic performance, as well as cost and size will be detailed. Some techniques to improve the above performance metrics will also be discussed.

A Low-Power Dual-Frequency SIMO Buck Converter Topology With Fully-Integrated Outputs and Fast Dynamic Operation in 45 nm CMOS

“…Conventional single-inductor multiple-output (SIMO) topologies [5]- [14] can be used to leverage the existing off-chip inductor to implement the additional power supplies needed by the system with better efficiency than linear regulators. However, their time-multiplexed power distribution results in poor cross-regulation between the multiple power supplies, and even slower output dynamic response and larger off-chip output capacitors than single-output topologies [15].…”

Variable Spurious Noise Mitigation Techniques in Hysteretic Buck Converters

“…With the growing demand for integrating digital, analog, and radio frequency (RF) sub-systems together in a single system-on-chip (SoC), power delivery to these diverse functions within an SoC has become more complex than ever [1]. A typical battery-operated mixed-signal SoC is shown in Fig.…”

“…This technique relies on a PWM sawtooth ramp signal that swings between constant upper and lower thresholds ( and ) while the frequency is hopped by changing the voltage slope (changing the charging current through a fixed capacitor). Assuming the switching frequency changes from (1) to (2) (switching period of (1) to (2) ) after time and that the sawtooth ramp signal is reset at that instance (goes to zero) as shown in Fig. 4.5, the duty-cycle can be expressed in terms of the ON time ( ) and as [34]:…”

“…4.7. The control signal is used to trigger a digital pseudo-random number generator which in turn randomly selects the switching frequency from a finite set of values (only two frequencies (1) and (2) are used here for simplicity). Using as the hopping signal instead of an external clock source in conjunction with fixing the PWM ramp signal swing results in minimizing duty-cycle disturbance [36].…”

“…This phase shift itself is also random due to the random selection of frequencies. Mathematically, the spurious component at the th harmonic of the first switching frequency (1) can be stated as [36]:…”