Power-Aware Optimization of SoC Test Schedules Using Voltage and Frequency Scaling

Sheshadri, Vijay; Agrawal, Vishwani D.; Agrawal, P.

doi:10.1007/s10836-017-5652-2

Cited by 3 publications

(1 citation statement)

References 36 publications

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“…For battery-operated system scaling, Dynamic Voltage and Frequency Scaling (DVFS) which is a voltage reduction method launched in the year 1990s [7], reduces energy usage utmost in big digital devices with the help of system's voltage and frequency adjustment for altering workloads. A regulated system equipped with DVFS can adjust a digital circuit's supply voltage at the functional boundary to the speed, temperature and parameters of the technology.…”

Section: Related Workmentioning

confidence: 99%

Energy-efficient Scheduling of Cloud Data Center Servers

Kumar¹,

Rani²

2019

IJITEE

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Data center is a cost-effective infrastructure to store large data volumes and host large-scale service applications. Providers of cloud computing services are deploying data centers worldwide quickly. With lots of servers and switches. These data centers consume substantial quantities of energy, which contributes to high operating costs. Optimizing server and network energy consumption in information centers can therefore decrease operating costs. In a data center, power utilization is chiefly because of servers, network devices, and cooling systems, an effective energy-saving strategy is to consolidate computing and communication into fewer servers and network devices and then power off as many unneeded servers and network devices as possible. A new method of reducing the energy utilization of computer systems and networks in data centers while meeting the requirements of the cloud tenants for quality of service (QoS) is proposed here in this paper.

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Section: Related Workmentioning

confidence: 99%

Energy-efficient Scheduling of Cloud Data Center Servers

Kumar¹,

Rani²

2019

IJITEE

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Thermal-aware SoC Test Scheduling with Voltage/Frequency Scaling and Test Partition

Zhang

Jiang

et al. 2018

J Electron Test

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A Strength Pareto Evolutionary Algorithm for Optimizing System-On-Chip Test Schedules

Marrouche

Farah

Harmanani

2018

Int. J. Comp. Intel. Appl.

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System-on-chip (SOC) has become a mainstream design practice that integrates intellectual property cores on a single chip. The SOC test scheduling problem maximizes the simultaneous test of all cores by determining the order in which various cores are tested. The problem is tightly coupled with the test access mechanism (TAM) bandwidth and wrapper design. This paper presents a strength Pareto evolutionary algorithm for the SOC test scheduling problem with the objective of minimizing the power-constrained test application time, wrapper design and TAM assignment in flat and hierarchical core-based systems. We demonstrate the effectiveness of the method using the ITC’02 benchmarks.

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Power-Aware Optimization of SoC Test Schedules Using Voltage and Frequency Scaling

Cited by 3 publications

References 36 publications

Energy-efficient Scheduling of Cloud Data Center Servers

Energy-efficient Scheduling of Cloud Data Center Servers

Thermal-aware SoC Test Scheduling with Voltage/Frequency Scaling and Test Partition

A Strength Pareto Evolutionary Algorithm for Optimizing System-On-Chip Test Schedules

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