Power/area/delay aware FSM synthesis and optimization

Shiue, Wen-Tsong

doi:10.1016/j.mejo.2004.10.009

Cited by 8 publications

(2 citation statements)

References 15 publications

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“…As the rapid increase in mobile system, the requirement of reducing power consumption in very large‐scale integration design has emerged [1, 2]. Finite‐state machine (FSM) is an important module in digital systems.…”

Section: Introductionmentioning

confidence: 99%

MPGA: an evolutionary state assignment for dynamic and leakage power reduction in FSM synthesis

Tao

Zhang

Wang

et al. 2018

IET Computers & Digital Techniques

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As the development of deep-submicron and nano-technology, leakage power minimisation becomes as important as dynamic power reduction in IC design. In order to achieve low-power state assignment for finite-state machine (FSM) synthesis, a multi-population genetic algorithm (MPGA)-based state assignment method is proposed. MPGA consists of an outer-loop and a set of inner-GAs. In MPGA, inner-GA is a local search component for finding low-power state assignment. Selection, crossover and mutation are used to perform variations on individuals. Cost function is defined based on power dissipation formulation of complementary metal oxide semiconductor (CMOS) gate for dynamic power and leakage power estimation. The outer-loop is used to optimise the parameters of inner-genetic algorithm (GA) through population variation schema, intra-specific competition and newborn. Twenty-three FSMs that were commonly used as benchmarks are employed to test the effectiveness of MPGA and compare different state assignment methods. Experimental results show MPGA achieves a significant improvement over the previous publications both on dynamic power and leakage power reduction in most benchmarks.

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Section: Introductionmentioning

confidence: 99%

MPGA: an evolutionary state assignment for dynamic and leakage power reduction in FSM synthesis

Tao

Zhang

Wang

et al. 2018

IET Computers & Digital Techniques

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“…Logic synthesis is the automated generation of an optimized logic networks (in terms of delay [1], area and/or power [2]) from another unoptimized/sub-optimized logic network. Over the years, many researchers have been interested in optimizing certain dedicated hardware components.…”

Section: Introductionmentioning

confidence: 99%

Tacue

Elbayoumi

Choudhury²,

Кравец³

et al. 2014

Proceedings of the 51st Annual Design Automation Conference

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Achieving timing-closure has become one of the hardest tasks in logic synthesis due to the required stringent timing constraints in very large circuit designs. In this paper, we propose a novel synthesis paradigm to achieve timing-closure called Timing-Aware CUt Enumeration (TACUE). In TACUE, optimization is conducted through three aspects: (1) a new divide-and-conquer strategy is proposed that generates multiple sub-cuts on the critical parts of the circuit; (2) two cut enumeration strategies are proposed; (3) an efficient parallel synthesis framework is offered to reduce computation time.Experiments on large and difficult industrial benchmarks show the promise of the proposed method.

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