Potential of low-resistivity Cu2Mg for highly scaled interconnects and its challenges

Chen, Linghan; Chen, Qian; Ando, Daisuke; Sutou, Yuji; Kubo, Momoji; Koike, Junichi

doi:10.1016/j.apsusc.2020.148035

Cited by 16 publications

(7 citation statements)

References 32 publications

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“…The dielectric constants were 2.56 ± 0.04 for p-SiOCH film and 3.62 ± 0.10 and 4.60 ± 0.08 for the SiCN films deposited at 100 °C and 300 °C, respectively. Assumed that no interaction exists during the integration of SiCN/p-SiOCH stacks, the ideal capacitances, based on Eq., 1 were calculated to be 1.306 × 10 -11 F and 1.390 × 10 -11 F for the staked dielectrics with the SiCN films deposited at 100 °C and 300 °C, respectively. In this study, the measured capacitances were 1.322 × 10 -11 F and 1.466 × 10 -11 F for the SiCN films deposited at 100 °C and 300 °C, respectively, which were larger than the theoretical values.…”

Section: Resultsmentioning

confidence: 99%

“…In order to reduce the resistance-capacitance signal delay and improve the performance of integrate circuits (ICs), Cu and porous low-dielectric-constant (low-k) materials have been replaced Al and SiO 2 in the back-end-of-line (BEOL) interconnects. [1][2][3][4] During the of Cu/porous low-k integration, the migration of Cu atoms/ions into the porous low-k insulating dielectric under an electrical stress or/and thermal stress is one of the critical issues, thus leading to the degradation of electrical properties and reliability. [5][6][7][8] To prevent such an issue, barriers are required to encapsulate Cu conductors.…”

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confidence: 99%

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Electrical Characteristics and Reliability of SiCN/Porous SiOCH Stacked Dielectric: Effects of Deposition Temperature of SiCN Film

Cheng

Lin

Peng

et al. 2021

ECS J. Solid State Sci. Technol.

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Silicon carbonitride (SiCN) films deposited using silazane singe-precursor with different temperatures were capped onto porous carbon-doped silicon oxide (p-SiOCH) dielectric films. Effects on the electrical and reliability characteristics of the fabricated SiCN/p-SiOCH stacked dielectrics were investigated. Experimental results indicated that increasing the deposition temperature of the SiCN film increased barrier capacity against Cu migration under thermal and electrical stress and time-dependence-dielectric-breakdown reliability for the SiCN/p-SiOCH stacked dielectric. Therefore, this study provides a promising processing to deposit a SiCN barrier by elevating the deposition temperature and using N-methyl-aza-2,2,4-trimethylsilacyclopentane singe-precursor, which can be applied to back-end-of-line interconnects for advanced technological nodes in the semiconductor industry. A larger capacitance, however, is the main issue due to a larger intrinsic dielectric constant of the SiCN film and stronger plasma-induced damage on the p-SiOCH film. As a result, the related actions will be taken in the future research to improve this issue.

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Section: Resultsmentioning

confidence: 99%

mentioning

confidence: 99%

Electrical Characteristics and Reliability of SiCN/Porous SiOCH Stacked Dielectric: Effects of Deposition Temperature of SiCN Film

Cheng

Lin

Peng

et al. 2021

ECS J. Solid State Sci. Technol.

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Section: Discussionmentioning

confidence: 99%

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confidence: 99%

Materials Quest for Advanced Interconnect Metallization in Integrated Circuits

et al. 2023

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Integrated circuits (ICs) are challenged to deliver historically anticipated performance improvements while increasing the cost and complexity of the technology with each generation. Front‐end‐of‐line (FEOL) processes have provided various solutions to this predicament, whereas the back‐end‐of‐line (BEOL) processes have taken a step back. With continuous IC scaling, the speed of the entire chip has reached a point where its performance is determined by the performance of the interconnect that bridges billions of transistors and other devices. Consequently, the demand for advanced interconnect metallization rises again, and various aspects must be considered. This review explores the quest for new materials for successfully routing nanoscale interconnects. The challenges in the interconnect structures as physical dimensions shrink are first explored. Then, various problem‐solving options are considered based on the properties of materials. New materials are also introduced for barriers, such as 2D materials, self‐assembled molecular layers, high‐entropy alloys, and conductors, such as Co and Ru, intermetallic compounds, and MAX phases. The comprehensive discussion of each material includes state‐of‐the‐art studies ranging from the characteristics of materials by theoretical calculation to process applications to the current interconnect structures. This review intends to provide a materials‐based implementation strategy to bridge the gap between academia and industry.

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“…As more exotic metal materials and compounds with complicated band structures are being considered for nanoscale interconnect applications [14,15,[27][28][29][30][31][32], their resistivity (scaling) can be expected to depend strongly on temperature and, for polycrystalline textured or single crystal interconnects, the orientation of the interconnect line with respect to the lattice orientation. Therefore, the usefulness of the ρλ product as a figure-of-merit can be questioned, as it does not capture the anisotropy of the charge carriers in the conduction band(s).…”

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confidence: 99%

First principles-based screening method for resistivity scaling of anisotropic metals

Moors¹,

Sankaran²,

Pourtois³

et al. 2021

Preprint

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The resistivity scaling of metals is a crucial factor for further downscaling of interconnects in nanoelectronic devices that affects signal delay, heat production, and energy consumption. Here, we present a screening method for metals with highly anisotropic band structures near the Fermi level with the aim to select promising materials in terms of their electronic transport properties and their resistivity scaling at the nanoscale. For this, we consider a temperature-dependent transport tensor, based on band structures obtained from first principles. This transport tensor allows for a straightforward comparison between different anisotropic metals in nanostructures with different lattice orientations. By evaluating the temperature dependence of the tensor components, we also find strong deviations from the zero-temperature transport properties at standard operating temperature conditions around room temperature.

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Potential of low-resistivity Cu2Mg for highly scaled interconnects and its challenges

Cited by 16 publications

References 32 publications

Electrical Characteristics and Reliability of SiCN/Porous SiOCH Stacked Dielectric: Effects of Deposition Temperature of SiCN Film

Electrical Characteristics and Reliability of SiCN/Porous SiOCH Stacked Dielectric: Effects of Deposition Temperature of SiCN Film

Materials Quest for Advanced Interconnect Metallization in Integrated Circuits

First principles-based screening method for resistivity scaling of anisotropic metals

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