Post-silicon debug using programmable logic cores

Abstract

Producing a functionally correct integrated circuit is becoming increasingly difficult. No matter how careful a designer is, there will always be integrated circuits that are fabricated, but do not operate as expected. Providing a means to effectively debug these integrated circuits is vital to help pin-point problems and reduce the number of re-spins required to create a correctly-functioning chip. In this paper, we show that programmable logic cores (PLCs) and flexible networks can provide this debugging capability. We present an architecture and example implementation. We show that the area overhead of this proposed architecture would be well below 10% for many target ICs.

Embedded Programmable Logic Core Enhancements for System Bus Interfaces

“…Other work has discussed integration without focusing on busses [14][15][16]. Finally, the current authors have described a post-silicon debug architecture that requires one or more SoC bus to PLC interfaces [1]. In this work it was assumed that the interface could be implemented using the logic provided by the PLC, however the cost and performance of the interface were not described.…”

“…A specific example of an application that requires this type of connectivity is post-silicon debug using programmable logic cores [1]. In this application the programmable logic allows debug circuits to be implemented so they interact with the various portions of the fixed function IP blocks.…”

“…These changes may be done to correct errors in the design or specification, to enable future upgrades, or to allow for the customization of an integrated circuit for multiple customers. Embedded Programmable Logic Cores (PLC's) can also provide a mechanism to add debug capability [1].…”

Software-Based Online Detection of Hardware Defects Mechanisms, Architectural Support, and Evaluation

“…Recently proposed solutions have considerable area overheads and still do not provide complete accessibility to the processor's state [23]. We believe the ACE framework can be an attractive low-overhead framework that provides the post-silicon debug engineers with full accessibility and controllability of the processor's internal state at runtime.…”

Asynchronous IC interconnect network design and implementation using a standard ASIC flow

“…The consideration of interconnect implementations presented in this paper is motivated by a larger project to develop an interconnect network to connect fixed logic blocks to a programmable logic core (PLC) in large SoCs to facilitate post-silicon debug [11]. While the details of the PLC application are not essential to this paper, there are a number of challenges presented by this application that make it a suitable candidate to explore inter-block interconnect implementations.…”