Post-reboot Equivalence and Compositional Verification of Hardware

Abstract

We introduce a finer concept of a Hardware Machine, where the set of post-reboot operation states is explicitly a part of the FSM definition. We formalize an ad-hoc flow of combinational equivalence verification of hardware, the way it was performed over the years in the industry. We define a concept of post-reboot bisimulation, which better suits the Hardware Machines, and show that a right form of combinational equivalence is in fact a form of post-reboot bisimulation. Further, we show that alignability equivalence is a form of post-reboot bisimulation, too, and the latter is a refinement of alignability in the context of compositional hardware verification. We find that post-reboot bisimulation has important advantages over alignability also in the wider context of formal hardware verification, where equivalence verification is combined with formal property verification and with validation of a reboot sequence. As a result, we propose a more comprehensive, compositional, and fullyformal framework for hardware verification. Our results are extendible to other forms of labeled transition systems and adaptable to other forms of bisimulation used to model and verify complex hardware and software systems.

Compositional verification of retiming and sequential optimizations

“…Recently, new compositional approaches on the alignability were introduced to deal with large designs, called weak alignability [7,8,12].…”

“…that often have different numbers of registers. Even though there have been many publications on sequential equivalence checking as in [13,5,20,18,19], the industry has started to use sequential equivalence checking only recently with practical approaches handling fairly large designs [7,8,1,12]. Baumgartner et al proposed sequential equivalence checking through a series of various transformations with a given reset state.…”

“…Baumgartner et al proposed sequential equivalence checking through a series of various transformations with a given reset state. Another practical method is a compositional approach on sequential equivalence checking, called weak alignability [7,8,12]. The original alignability was introduced by Pixley as a good notion of sequential equivalence without a known reset state [13].…”

A Compositional Approach to the Combination of Combinational and Sequential Equivalence Checking of Circuits Without Known Reset States

“…In independent research to the work presented here, Khasidashvili and coworkers recently presented a revised equivalence checking method that aim to integrate combinational and sequential equivalence checking in a compositional manor [5]. In contrast to our approach, the work in [5] presupposes knowledge of a sequence that is used to force a design into a set of post-reboot "good" states.…”

“…In contrast to our approach, the work in [5] presupposes knowledge of a sequence that is used to force a design into a set of post-reboot "good" states. As our method is aimed at integration in an traditional combinational equivalence checking environment, we do not require this information (but we could use it to prove weak synchronizability or I/O equivalence in a compositional manor, if we had it available).…”