Post-placement C-slow retiming for the xilinx virtex FPGA

Weaver, Nicholas; Markovskiy, Yury; Patel, Yatish; Wawrzynek, John

doi:10.1145/611817.611845

Cited by 42 publications

(25 citation statements)

References 6 publications

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“…The second assumption allows us to use high-latency pipelined functional units to achieve high clock rates while still achieving high throughput, by using the C-Slow approach [Weaver et al 2003]. …”

Section: Mapping Tree-based Models To Hardwarementioning

confidence: 99%

Exploring Reconfigurable Architectures for Tree-Based Option Pricing Models

Jin

Thomas

Luk

et al. 2009

ACM Trans. Reconfigurable Technol. Syst.

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This article explores the application of reconfigurable hardware to the acceleration of financial computation using tree-based pricing models. Two parallel pipelined architectures have been developed for option valuation using binomial trees and trinomial trees, with support for concurrent evaluation of independent options to achieve high pricing throughput. Our results show that the tree-based models executing on a Virtex 4 field programmable gate array (FPGA) at 82.7 MHz with fixed-point arithmetic can run over 160 times faster than a Core2 Duo processor at 2.2 GHz. The FPGA implementation is two times faster than the nVidia Geforce 7900GTX processor with 24 pipelines at 650 MHz, and 27%-35% slower than the nVidia Geforce 8600GTS processor with 32 Pipelines at 1450 MHz. Our preliminary experiments also indicate that while an FPGA implementation can be slower than a GPU, it could be more efficient when power consumption is taken into account.

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Section: Mapping Tree-based Models To Hardwarementioning

confidence: 99%

Exploring Reconfigurable Architectures for Tree-Based Option Pricing Models

Jin

Thomas

Luk

et al. 2009

ACM Trans. Reconfigurable Technol. Syst.

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show abstract

“…Works such as [15] and [8] have attempted to address FPGA-specific concerns. [15] suggests a two-phase approach.…”

Section: Previous Cad Solutionsmentioning

confidence: 99%

“…[15] suggests a two-phase approach. The authors begin with a full simulated annealing placement, but then retiming is performed without any restrictions on the number of registers that can be placed on a given link.…”

Section: Previous Cad Solutionsmentioning

confidence: 99%

Simultaneous Retiming and Placement for Pipelined Netlists

Eguro

Hauck

2008

2008 16th International Symposium on Field-Programmable Custom Computing Machines

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“…Multiple simulation paths can then be scheduled in a C-Slow fashion [4], with as many paths as can be accommodated by the pipelined update function proceeding in parallel. As states exit the transition function pipeline, they can be checked against the termination condition.…”

Section: Design Flowmentioning

confidence: 99%