Possibilities of deep-submicrometer CMOS for very-high-speed computer logic

Masaki, Akira

doi:10.1109/5.237538

Cited by 20 publications

(2 citation statements)

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“…GENESYS extends the capabilities of previous system-level performance simulators [7], [22], [23], allowing a more thorough exploration of the entire hierarchy of physical and practical limits. While other simulators focus exclusively on interconnect technology [24], GENESYS describes the complete chip design for a more realistic investigation.…”

Section: Related Workmentioning

confidence: 99%

Heterogeneous architecture models for interconnect-motivated system design

Chai

Taha

Wills

et al. 2000

IEEE Trans. VLSI Syst.

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On-chip interconnect demand is becoming the dominant factor in modern processor performance and must be estimated early in the design process. This paper presents a set of heterogeneous architectural models that combines architecture description and Rent's Rule-based wiring models. These architecture models allow flexible heterogeneous system specifications, enabling investigations of prospective designs in different technology scenarios. Comparisons against actual data demonstrate the models' effectiveness for architecture explorations with highly accurate estimations of local and global wiring demand, as well as chip area and cycle time. Simulation of two candidate system designs reveal trends in interconnect delay with increasing architectural complexity, and confirm the need for high computational locality and short global wires for future architectures.

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Section: Related Workmentioning

confidence: 99%

Heterogeneous architecture models for interconnect-motivated system design

Chai

Taha

Wills

et al. 2000

IEEE Trans. VLSI Syst.

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show abstract

“…20 the system switching energy limit is defined by a composite gate which characterizes the critical path of a macrocell. For a logic signal this path is assumed to consist of 1) a chain of n cp random logic gates and 2) one macrocell corner-to-corner global interconnect of length 2L [56], [57]. Therefore, the prorata switching energy of the composite gate is given by…”

Section: E System Limitsmentioning

confidence: 99%