Positive feedback CMOS charge-pump circuits for PLL applications

Hernandez, Esdras Juarez; Sánchez, Agustín Rueda

doi:10.1109/mwscas.2001.986317

Cited by 6 publications

(1 citation statement)

References 7 publications

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“…As shown in [3][4][5][6] in the special case of a divide-by-two and a third-order nonlinearity, the phase-limited locking range of an LC ILFD can be expressed as:…”

Section: B Frequency Dividersmentioning

confidence: 99%

A 5.2GHz CMOS fractional-n frequency synthesizer with a MASH delta-sigma modulator

Chen

Liou

et al. 2008

2008 51st Midwest Symposium on Circuits and Systems

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A 5-GHz CMOS fractional-N frequency synthesizer with a delta-sigma modulator is designed in this paper. The frequency dividers are composed of an injection-locked frequency divider and a programmable divider. In consideration of low power consumption, we use an injection-locked frequency divider as the first stage prescaler. The loop filter is a second-order passive filter. The delta-sigma modulator is MASH 1-1-1 architecture. The VCO exhibits a phase noise of-116dBc/Hz at 1MHz offset frequency and an output frequency ranges from 4.91GHz to 5.38GHz. TSMC 0.18-μm CMOS process is used for this frequency synthesizer design and simulation. The frequency resolution of this fractional-N frequency synthesizer is 27 KHz and the locking time is 8 μs. Keywords-frequency synthesizer; delta-sigma modulator; MASH 1-1-1 architecture; 0.18-μm CMOS process.

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“…As shown in [3][4][5][6] in the special case of a divide-by-two and a third-order nonlinearity, the phase-limited locking range of an LC ILFD can be expressed as:…”

Section: B Frequency Dividersmentioning

confidence: 99%

A 5.2GHz CMOS fractional-n frequency synthesizer with a MASH delta-sigma modulator

Chen

Liou

et al. 2008

2008 51st Midwest Symposium on Circuits and Systems

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A new CMOS charge pump for low-voltage (1V) high-speed PLL applications

Baki

El-Gamal

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03.

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A 1.35 GHz CMOS wideband frequency synthesizer for mobile communications

Juarez-Hernandez

Díaz-Sánchez²,

Tleio-Cuautle³

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03.

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The design and simulation of a 1.35 GHz fully integrated CMOS frequency synthesizer for a double band receiver is presented. The proposed synthesizer is based on a wide-band PLL topology with a high reference frequency. This approach allows obtaining low phase noise, fast switching time, a low divider ratio and a reduction in the total chip area. Besides, the use of a novel charge-pump circuit with partial positive feedback and current reuse allows a further reduction in both chip area and power consumption, making the proposed structure suitable for high frequency and low-voltage phase-locked loops.

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Positive feedback CMOS charge-pump circuits for PLL applications

Cited by 6 publications

References 7 publications

A 5.2GHz CMOS fractional-n frequency synthesizer with a MASH delta-sigma modulator

A 5.2GHz CMOS fractional-n frequency synthesizer with a MASH delta-sigma modulator

A new CMOS charge pump for low-voltage (1V) high-speed PLL applications

A 1.35 GHz CMOS wideband frequency synthesizer for mobile communications

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