A 1.35 GHz CMOS wideband frequency synthesizer for mobile communications

Abstract

The design and simulation of a 1.35 GHz fully integrated CMOS frequency synthesizer for a double band receiver is presented. The proposed synthesizer is based on a wide-band PLL topology with a high reference frequency. This approach allows obtaining low phase noise, fast switching time, a low divider ratio and a reduction in the total chip area. Besides, the use of a novel charge-pump circuit with partial positive feedback and current reuse allows a further reduction in both chip area and power consumption, making the proposed structure suitable for high frequency and low-voltage phase-locked loops.

An integer-N frequency synthesizer for medical implantable devices

“…In Figure 5.4 when the "UpPositive"(signal "B") pulse width is high, the transistor M84 is on and the current mirror transistors M83 and M81 are also on. The current that passes through transistor The dead zone phenomenon happens when there is no output from the charge pump in response to the phase error at the input of the PFD [26]. The usual cause of the dead zone is the sluggish response of the charge pump current switches reaction to the "UpPositve"(signal B)and "DownPositive"(Signal A) coming from the PFD.…”