Positive Bias Temperature Instability Effects in nMOSFETs With $\hbox{HfO}_{2}/\hbox{TiN}$ Gate Stacks

Ioannou, D.P.; Mittl, S.; Rosa, G. La

doi:10.1109/tdmr.2009.2020432

Cited by 29 publications

(14 citation statements)

References 15 publications

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“…This time has the same mathematical form as the definition of the duty cycle fraction in an AC experiment. The fraction remaining, FR, has previously been used for the modeling of the NBTI recovery [5,9] and more recently it has been found to show good scalability for PBTI recovery as well [7,10]. This is also demonstrated by our data in Fig.…”

Section: Pbti Fractional Recovery Vs Il Thickness (Uninterrupted supporting

confidence: 80%

“…To study the impact of the IL thickening on PBTI, three different measurement techniques were used; 1) a recently proposed Voltage Ramp Stress (VRS) methodology [6], 2) a fast Constant Voltage Stress (CVS) [7] and 3) an uninterrupted CVS method (proposed here) featuring uninterrupted stresses at various stress times (t stress ) followed by a prolonged recovery monitor phase of fixed duration. Fig.…”

Section: B Measurementsmentioning

confidence: 99%

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PBTI response to interfacial layer thickness variation in Hf-based HKMG nFETs

Ioannou

Cartier

Wang

et al. 2010

2010 IEEE International Reliability Physics Symposium

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The impact of SiO 2 interfacial layer (IL) thickness on the Positive Bias Temperature Instability (PBTI) is investigated for nMOSFETs with an IL/High-K/metal/poly-Si gate stack architecture. Results from extensive PBTI measurements using three different measurement methodologies consistently demonstrate that thickening the IL results in threshold voltage (V T ) instability reduction and thus significantly enhances PBTI device lifetime. The voltage acceleration is found to increase with thicker IL, while the PBTI fractional recovery is independent of the IL thickness, providing new insights into the PBTI buildup and recovery mechanisms.

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Section: Pbti Fractional Recovery Vs Il Thickness (Uninterrupted supporting

confidence: 80%

Section: B Measurementsmentioning

confidence: 99%

PBTI response to interfacial layer thickness variation in Hf-based HKMG nFETs

Ioannou

Cartier

Wang

et al. 2010

2010 IEEE International Reliability Physics Symposium

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“…The V t instability and the SILC formation in nFETs with SiO 2 /HfO 2 /metal gate stacks under positive-bias temperature (PBT) stress have been previously studied in some detail [1][2][3][4][5][6][7][8][9][10]. Both degradation phenomena have been related to electron trapping in bulk oxide defects and oxygen vacancies in the HfO 2 layer were proposed as one of the primary defects [1,2].…”

Section: Introductionmentioning

confidence: 99%

Stress-induced leakage current and defect generation in nFETs with HfO<inf>2</inf>/TiN gate stacks during positive-bias temperature stress

Cartier

Kerber

2009

2009 IEEE International Reliability Physics Symposium

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The stress-induced leakage current (SILC) in nFETs with SiO 2 /HfO 2 /TiN dual-dielectric gate stacks with metal electrodes is studied during positive-bias temperature stress at high temperatures and at high gate stress voltage. It is shown that strong defect creation in the HfO 2 causes a linear increase of the SILC with stress time. The SILC generation is found to be thermally activated with an activation energy, E a ~ 1 eV. In addition, the SILC formation exhibits a strong correlation with the threshold voltage (V t ) instability ΔI g /I g ~ dV t 3 . Both degradation phenomena show a strong hysteretic behavior with gate bias; the SILC and V t -degradation are observed to be substantially reduced by applying a negative gate bias after stress. All these observations may be rationalized in terms of charge trapping in shallow HfO 2 defects -such as oxygen vacancy -and by the generation of new shallow defects during stress. The defect generation process has a low activation energy, likely because of thin-film effects. Therefore, the SILC and the V t instability are large under accelerated TDDB test conditions. It is also shown that the observed low activation energy in combination with the reversibility of the SILC has important implications for dielectric breakdown detection in dual-dielectric gate stacks.

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“…Once the applied gate and drain biases are removed, a partial recovery of the threshold voltage shift occurs. Previous works ascribed this effect to electron de-trapping from oxide bulk defects, and identify the amount of recoverable shift as a parasitic BTI component included in CHC stress [6], [7], and [8]. In this paper, we show that the threshold voltage recovery can be induced by the de-trapping of electrons which were injected due to both the parasitic PBTI effect (cold carrier) and the intrinsic hot carrier effect (i.e., carrier generated by impact ionization) [9], [10].…”

Section: Impact Of the Substrate Orientation On Chc Reliability In N-mentioning

confidence: 99%

Impact of the Substrate Orientation on CHC Reliability in n-FinFETs—Separation of the Various Contributions

Tallarico

Cho

Franco

et al. 2014

IEEE Trans. Device Mater. Relib.

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In this paper, we perform a comparative analysis of the degradation induced by a channel hot carrier (CHC) in bulk n-FinFETs with rotated (100) and nonrotated (110) sidewall surfaces. CHC degradation includes several components, and separating each contribution is necessary for identifying different mechanisms in devices with different surface orientations. First, the permanent and recoverable components are separated based on the recovery phenomenon after the CHC stress, ascribed to the electron detrapping from the oxide bulk defects. Then, the contribution of generated interface states to the permanent component is quantified by charge pumping measurements. The nonrotated bulk FinFETs showed higher threshold voltage degradation at the maximum bulk current stress condition due to the higher interface precursor defect density compared with the rotated devices. On the other hand, the rotated bulk FinFETs showed higher threshold voltage degradation at the stress condition of V G = V D due to higher bulk defect trapping, ascribed to the lower physical oxide thickness.

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Positive Bias Temperature Instability Effects in nMOSFETs With $\hbox{HfO}_{2}/\hbox{TiN}$ Gate Stacks

Cited by 29 publications

References 15 publications

PBTI response to interfacial layer thickness variation in Hf-based HKMG nFETs

PBTI response to interfacial layer thickness variation in Hf-based HKMG nFETs

Stress-induced leakage current and defect generation in nFETs with HfO<inf>2</inf>/TiN gate stacks during positive-bias temperature stress

Impact of the Substrate Orientation on CHC Reliability in n-FinFETs—Separation of the Various Contributions

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