Polyimide based temporary wafer bonding technology for high temperature compliant TSV backside processing and thin device handling

Zoschke, Kai; Fischer, Thorsten; Topper, Michael J.; Fritzsch, T.; Ehrmann, O.; Itabashi, Toshiaki; Zussman, Melvin P.; Souter, Matthew; Oppermann, Hermann; Lang, Klaus‐Dieter

doi:10.1109/ectc.2012.6248966

Cited by 30 publications

(10 citation statements)

References 8 publications

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“…The quad modules employ a 200 µm thick sensor interconnected to four FE-I4 chips that have been thinned down to 150 µm at IZM. A glass substrate has been attached to the chip backside to avoid the bending of the corners after thinning, that could lead to a decrease of the bump-bonding efficiency [16]. The modules have an inactive area in the 1.6 mm gap between the rows of the two double sensors, where the GR and BR structures are located.…”

Section: Four Chip Module Characterizationmentioning

confidence: 99%

Thin n-in-p planar pixel sensors and active edge sensors for the ATLAS upgrade at HL-LHC

Terzo¹,

Macchiolo²,

Nisius³

et al. 2014

J. Inst.

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Silicon pixel modules employing n-in-p planar sensors with an active thickness of 200 µm, produced at CiS, and 100-200 µm thin active/slim edge sensor devices, produced at VTT in Finland have been interconnected to ATLAS FE-I3 and FE-I4 read-out chips. The thin sensors are designed for high energy physics collider experiments to ensure radiation hardness at high fluences. Moreover, the active edge technology of the VTT production maximizes the sensitive region of the assembly, allowing for a reduced overlap of the modules in the pixel layer close to the beam pipe. The CiS production includes also four chip sensors according to the module geometry planned for the outer layers of the upgraded ATLAS pixel detector to be operated at the HL-LHC. The modules have been characterized using radioactive sources in the laboratory and with high precision measurements at beam tests to investigate the hit efficiency and charge collection properties at different bias voltages and particle incidence angles. The performance of the different sensor thicknesses and edge designs are compared before and after irradiation up to a fluence of 1.4×10 16 n eq /cm 2 .

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Section: Four Chip Module Characterizationmentioning

confidence: 99%

Thin n-in-p planar pixel sensors and active edge sensors for the ATLAS upgrade at HL-LHC

Terzo¹,

Macchiolo²,

Nisius³

et al. 2014

J. Inst.

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“…Mainstream bonding adhesives include benzocyclobutene (BCB) [144]- [147], polyimide [148]- [150], epoxy resin [151], [152], as well as many other polymers [153], [154]. BCB has become a widely-used bonding adhesive in 3-D integration and MEMS [13], [155], [156] due to its good chemical resistance, high bonding strength, low out-gassing, good thermal stability, ease of patterning, and desirable dielectric properties.…”

Section: ) Emerging Materials and Methodsmentioning

confidence: 99%

3-D Integration and Through-Silicon Vias in MEMS and Microsensors

Wang

2015

J. Microelectromech. Syst.

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After two decades of intensive development, 3-D integration has proven invaluable for allowing integrated circuits to adhere to Moore's Law without needing to continuously shrink feature sizes. The 3-D integration is also an enabling technology for hetero-integration of microelectromechanical systems (MEMS)/microsensors with different technologies, such as CMOS and optoelectronics. This 3-D heterointegration allows for the development of highly integrated multifunctional microsystems with small footprints, low cost, and high performance demanded by emerging applications. This paper reviews the following aspects of the MEMS/ microsensor-centered 3-D integration: fabrication technologies and processes, processing considerations and strategies for 3-D integration, integrated device configurations and wafer-level packaging, and applications and commercial MEMS/ microsensor products using 3-D integration technologies. Of particular interest throughout this paper is the heterointegration of the MEMS and CMOS technologies. [2015-0158]Index Terms-Three-dimensional (3-D) integration, microelectromechanical systems (MEMS), microsensor, packaging, hetero-integration, interposer, through-silicon-via (TSV), waferlevel packaging, microsystem.

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“…release by laser ablation of glue through transparent carrier wafers [8,9] 2. release by glue dissolution with solvent through perforated carrier wafers [10,11] 3. mechanical release by slide-off at elevated temperatures due to low viscosity of glue [12,13] 4. mechanical release by tilting due to low adhesion of glue at bond interface [14,15] The suitable temporary carrier solution needs to be chosen carefully depending on the complexity of backside processing, the kind of front side topography and the kind of the final assembly method. In each case, the chosen carrier solution needs to be highly flexible in use and robust to give an optimal support for the corresponding thin wafer processing and handling task.…”

Section: Figure 1: Schematic Process Flow For Silicon Interposer Fabrmentioning

confidence: 99%

Wafer level 3D system integration based on silicon interposers with through silicon vias

Zoschke

Oppermann

Manier

et al. 2012

2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)

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This paper presents a detailed description of the fabrication steps for wafer level processing of silicon interposers with copper filled TSVs as well as their subsequent assembly treatment. The electrical performance and characterization of the TSVs is also discussed. The interposers are created at 200 mm or 300 mm silicon wafers. The fabrication processes include deep reactive ion etching, TSV side wall isolation, PVD seed layer deposition, TSV filling by copper electroplating, wafer front side redistribution, temporary wafer bonding, wafer thinning by mechanical grinding, CMP, silicon dry etching, PECVD, silicon oxide dry etching and wafer backside redistribution. Depending on the final device application, after backside processing a component assembly is done directly at the interposer backside. In other cases, the interposer wafers are either released from the carrier wafers or transfer bonded so that their front side can be accessed again and the component assembly can be done. Finally, the assembled interposers can be release from their carrier wafers and singulated or run into further processes like molding or hermetic sealing by wafer to wafer bonding using suitable capwafers. In the following sections, important technological aspects of interposer fabrication and assembly as well as results from electrical characterizations will be presented. Detailed discussion of produced evaluation devices will explain and outline the versatility of the silicon interposer approach to be a flexible base technology for different application scenarios

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Polyimide based temporary wafer bonding technology for high temperature compliant TSV backside processing and thin device handling

Cited by 30 publications

References 8 publications

Thin n-in-p planar pixel sensors and active edge sensors for the ATLAS upgrade at HL-LHC

Thin n-in-p planar pixel sensors and active edge sensors for the ATLAS upgrade at HL-LHC

3-D Integration and Through-Silicon Vias in MEMS and Microsensors

Wafer level 3D system integration based on silicon interposers with through silicon vias

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