Polyhedral model based mapping optimization of loop nests for CGRAs

Abstract

The coarse-grained reconfigurable architecture (CGRA) is a promising platform that provides both high performance and high power-efficiency. The compute-intensive portions of an application (e.g. loops) are often mapped onto CGRA for acceleration. To optimize the mapping of loop nests to CGRA, this paper makes two contributions: i) Establishing a precise CGRA performance model and formulating the loop nests mapping as a nonlinear optimization problem based on polyhedral model, ii) Extracting an efficient heuristic loop transformation and mapping algorithm (PolyMAP) to improve mapping performance. Experiment results on most kernels of the PolyBench and real-life applications show that our proposed approach can improve the performance of the kernels by 21% on average, as compared to one of the best existing mapping algorithm, EPIMap. The runtime complexity of PolyMAP is also acceptable.

Battery-Aware Loop Nests Mapping for CGRAs

“…First, the loop nest is unrolled and an iteration domain is derived from the bounds of loops [9], where each node denotes an iteration (loop body); next, the iteration domain is tiled into small loop tiling blocks; finally each block is mapped onto PEA in the left-to-right and top-to-bottom order. Here we use the PEA resource tile (PRT) defined in [6] to describe the mapping relationship between PEA and the iteration domain. The PRT indicates the maximal size of iterations a PEA could hold, and each PRT refers to a PEA operation of CGRA.…”

“…When all the durations of every PEA operation are determined, we will obtain the start time of each PEA operation, denoted as t p . According to [6], each duration is determined by the form of loop nests mapping, so finding a suitable mapping method is the objective.…”

“…4 (b). Like the work in [6], we define Regular PRT (R-PRT) as PRT full filled with iterations, and define Irregular PRT (I-PRT) as PRT partial filled with iterations. Figure 4 (c) uses the blue tiles and the yellow tiles to represent R-PRTs and I-PRTs respectively.…”

“…In [5], a method called EPIMap is proposed to obtain optimal mapping scheme, which uses recomputation for resource limitation and obtained optimized II for a single-level loop and is based on modulo scheduling. In [6], the proposed approach called PolyMap uses polyhedral model to do mapping optimization of nested loop, where only the total execution time of CGRA is taken as an optimization metric and regardless of energy consumption. In [7], the active area of FPGA is considered as a key…”

Coarse-grained reconfigurable architecture with hierarchical context cache structure and management approach

“…Besides the hardware structure of CGRA, the configuration process plays an increasingly important role in terms of improving performance and reducing power consumption [10,11,12]. The proposed CGRA features dynamic configuration, where no more configuration contexts are updated during its computation.…”