Polyhedral-based data reuse optimization for configurable computing

Pouchet, Louis-Noël; Zhang, Peng; Sadayappan, P.; Cong, Jason

doi:10.1145/2435264.2435273

Cited by 142 publications

(110 citation statements)

References 44 publications

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“…This idea is further extended with multiple transformations as the polyhedral model from [14]. In [15] Compared to [15], our accelerator is more flexible because it is programmable with configuration words, such that varying workloads can be used.…”

Section: Related Workmentioning

confidence: 99%

Memory-centric accelerator design for Convolutional Neural Networks

Peemen

Setio

Mesman

et al. 2013

2013 IEEE 31st International Conference on Computer Design (ICCD)

282

153

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Abstract-In the near future, cameras will be used everywhere as flexible sensors for numerous applications. For mobility and privacy reasons, the required image processing should be local on embedded computer platforms with performance requirements and energy constraints. Dedicated acceleration of Convolutional Neural Networks (CNN) can achieve these targets with enough flexibility to perform multiple vision tasks. A challenging problem for the design of efficient accelerators is the limited amount of external memory bandwidth. We show that the effects of the memory bottleneck can be reduced by a flexible memory hierarchy that supports the complex data access patterns in CNN workload. The efficiency of the on-chip memories is maximized by our scheduler that uses tiling to optimize for data locality. Our design flow ensures that on-chip memory size is minimized, which reduces area and energy usage. The design flow is evaluated by a High Level Synthesis implementation on a Virtex 6 FPGA board. Compared to accelerators with standard scratchpad memories the FPGA resources can be reduced up to 13x while maintaining the same performance. Alternatively, when the same amount of FPGA resources is used our accelerators are up to 11x faster.

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Section: Related Workmentioning

confidence: 99%

Memory-centric accelerator design for Convolutional Neural Networks

Peemen

Setio

Mesman

et al. 2013

2013 IEEE 31st International Conference on Computer Design (ICCD)

282

153

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“…Recently a new tool is developed that optimizes HLS input descriptions for parallelism and locality [14]. This method uses the polyhedral framework for transformations and uses a HLS tool such as Vivado HLS (former AutoESL) to estimate the quality of result.…”

Section: Related Workmentioning

confidence: 99%

“…We use the models proposed in Section IV to obtain the best schedules, and this will take only seconds instead of hours or days as reported by other search methods [14], [12]. This target is achieved by using analytical models that can be evaluated quickly, and using inter-tile reuse optimization, which prunes the search space.…”

Section: Scheduling Space Explorationmentioning

confidence: 99%

Inter-Tile Reuse Optimization Applied to Bandwidth Constrained Embedded Accelerators

Peemen

Mesman

Corporaal

2015

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2015

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Abstract-The adoption of High-Level Synthesis (HLS) tools has significantly reduced accelerator design time. A complex scaling problem that remains is the data transfer bottleneck. To scale-up performance accelerators require huge amounts of data, and are often limited by interconnect resources. In addition, the energy spent by the accelerator is often dominated by the transfer of data, either in the form of memory references or data movement on interconnect. In this paper we drastically reduce accelerator communication by exploration of computation reordering and local buffer usage. Consequently, we present a new analytical methodology to optimize nested loops for intertile data reuse with loop transformations like interchange and tiling. We focus on embedded accelerators that can be used in a multi-accelerator System on Chip (SoC), so performance, area, and energy are key in this exploration. 1) On three common embedded applications in the image/video processing domain (demosaicing, block matching, object detection), we show that our methodology reduces data movement up to 2.1x compared to the best case of intra-tile optimization. 2) We demonstrate that our small accelerators (1-3% FPGA resources) can boost a simple MicroBlaze soft-core to the performance level of a high-end Inteli7 processor.

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“…In the past, polyhedral models have been used for maximizing parallelism while minimizing communcation for parallel computing [18,2]. Recently, polyhedral models have been used in high level synthesis for FPGAs to optimize on-chip memory bandwidth [12,21], or to optimize the SDRAM bandwidth [3]. In contrast, our approach is to optimize multiple data-dependent blocks simultaneously in order to match their data access patterns and thus simultaneously optimize both intra-block parallelism and inter-block pipelining.…”

Section: Related Workmentioning

confidence: 99%

Improving high level synthesis optimization opportunity through polyhedral transformations

Zuo

Liang

et al. 2013

Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays

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High level synthesis (HLS) is an important enabling technology for the adoption of hardware accelerator technologies. It promises the performance and energy efficiency of hardware designs with a lower barrier to entry in design expertise, and shorter design time. State-of-the-art high level synthesis now includes a wide variety of powerful optimizations that implement efficient hardware. These optimizations can implement some of the most important features generally performed in manual designs including parallel hardware units, pipelining of execution both within a hardware unit and between units, and fine-grained data communication. We may generally classify the optimizations as those that optimize hardware implementation within a code block (intra-block) and those that optimize communication and pipelining between code blocks (interblock). However, both optimizations are in practice difficult to apply. Real-world applications contain data-dependent blocks of code and communicate through complex data access patterns. Existing high level synthesis tools cannot apply these powerful optimizations unless the code is inherently compatible, severely limiting the optimization opportunity.In this paper we present an integrated framework to model and enable both intra-and inter-block optimizations. This integrated technique substantially improves the opportunity to use the powerful HLS optimizations that implement parallelism, pipelining, and fine-grained communication. Our polyhedral model-based technique systematically defines a set of data access patterns, identifies effective data access patterns, and performs the loop transformations to enable the intra-and inter-block optimizations. Our framework automatically explores transformation options, performs code transformations, and inserts the appropriate HLS directives to implement the HLS optimizations. Furthermore, our framework can automatically generate the optimized communication blocks for fine-grained communication between hardware blocks. Experimen- * Corresponding Author Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. FPGA '13, February 11-13, 2013, Monterey, California, USA. Copyright 2013 ACM 978-1-4503-1887 tal evaluation demonstrates that we can achieve an average of 6.04X speedup over the high level synthesis solution without our transformations to enable intra-and inter-block optimizations.

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Polyhedral-based data reuse optimization for configurable computing

Cited by 142 publications

References 44 publications

Memory-centric accelerator design for Convolutional Neural Networks

Memory-centric accelerator design for Convolutional Neural Networks

Inter-Tile Reuse Optimization Applied to Bandwidth Constrained Embedded Accelerators

Improving high level synthesis optimization opportunity through polyhedral transformations

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