2020
DOI: 10.1016/j.mee.2019.111157
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Polydimethylsiloxane as polymeric protective coating for fabrication of ultra-thin chips

Abstract: The bendable silicon-based ultra-thin chips (UTCs), with thickness below 50 μm are needed to provide high-performance flexible electronics for several emerging applications ranging from flexible displays to robotic e-skin. The UTCs from standard silicon wafer are obtained by etching the bulk material from the backside of the wafer using a wet chemical etchant. During the etching process, it is imperative to protect the front processed side from the etchant as in most cases, the etchant is incompatible with the… Show more

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Cited by 16 publications
(9 citation statements)
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References 44 publications
(51 reference statements)
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“…The UTCs are typical example of macrostructures that are obtained by physical or chemical removal of bulk silicon through top-down approaches [49]. Various methodologies used for obtaining UTCs include grinding, controlled spalling technique (CST), dry etching, and wet etching [26,49,[125][126][127][128][129][130][131]. Briefly, the CST is a slim cut process in which thin silicon layer is removed or exfoliated from the bulk silicon chip; the tensile Ni stressor layer is deposited on bulk chip and shear force is applied to generate stress induced parallel fracture along the surface of bulk chip [127].…”
Section: Chip Scale Structures-ultra-thin Chipsmentioning
confidence: 99%
See 3 more Smart Citations
“…The UTCs are typical example of macrostructures that are obtained by physical or chemical removal of bulk silicon through top-down approaches [49]. Various methodologies used for obtaining UTCs include grinding, controlled spalling technique (CST), dry etching, and wet etching [26,49,[125][126][127][128][129][130][131]. Briefly, the CST is a slim cut process in which thin silicon layer is removed or exfoliated from the bulk silicon chip; the tensile Ni stressor layer is deposited on bulk chip and shear force is applied to generate stress induced parallel fracture along the surface of bulk chip [127].…”
Section: Chip Scale Structures-ultra-thin Chipsmentioning
confidence: 99%
“…In addition, it is challenging to completely remove the stressor layer. Another popular and broadly utilized thinning approach is back grinding technique, in which the grinding wheel is used to physically dislodge the back/bottom side of silicon to reduce the thickness of bulk silicon down to less than 10 μm with in few minutes [130,132]. However, the stress induced during the grinding process could alter the silicon crystalline structure resulting in undesirable warping.…”
Section: Chip Scale Structures-ultra-thin Chipsmentioning
confidence: 99%
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“…The surface structures of PDMS devices can be modified either using dry or wet etching [22], and wet etching has been reported to be a quicker process than dry etching [23]. Tetrabutylammonium fluoride (TBAF) is a prevalent wet etchant that is used to etch PDMS [24][25][26][27], for which its mechanism involves the naked fluoride ion in TBAF attacking the siloxane bond in PDMS [26], [28]. Although the effect of the surface roughness on optical property has importance, only a few studies about the surface roughness of the microchannel wall exist and those reported, are in the aspects of effects on fluid flow and thermal transport characteristics.…”
Section: Introductionmentioning
confidence: 99%