Poly-Silicon Trap Position and Pass Voltage Effects on RTN Amplitude in a Vertical NAND Flash Cell String

Chou, Yi-Teh; Wang, Tahui; Lin, Mercator; Chang, YoungChul; Liu, Lenvis; Huang, Shih-Cheng; Tsai, Wen-Jer; Lu, Tsung-Chien; Chen, K. C.; Lu, Chih‐Yuan

doi:10.1109/led.2016.2585860

Cited by 17 publications

(10 citation statements)

References 10 publications

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“…Data show that the tail slope of the bitline current increases as the pass voltage is increased. This result was related to the previous one by the authors of [ 122 ], as increasing the pass voltage means a reduction of the read threshold voltage and an increase in the RTN fluctuations. However, further analysis are needed to clarify the link between the string operating conditions and the measured RTN.…”

Section: Experimental Datasupporting

confidence: 86%

“…This kind of fluctuations in poly-Si channels were first shown (to our knowledge) in [ 118 ], on a nanowire structure (no filler oxide), showing an exponential distribution for

, which is a typical result of a percolation process. The same exponential dependence was reported on vertical NAND devices in [ 119 , 120 , 121 , 122 , 123 ], suggesting that the RTN distribution in arrays follows an

law, and can be effectively characterized by the slope

of the exponential distribution.…”

Section: Experimental Datasupporting

confidence: 72%

“…Additional dependences exhibited by random telegraph noise in 3D NAND were reported by [ 108 , 122 ] with reference to read current and pass voltage. Figure 6 (left) shows RTN data for cells on different wordlines as a function of the read current and pass voltage.…”

Section: Experimental Datamentioning

confidence: 75%

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Random Telegraph Noise in 3D NAND Flash Memories

et al. 2021

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In this paper, we review the phenomenology of random telegraph noise (RTN) in 3D NAND Flash arrays. The main features of such arrays resulting from their mainstream integration scheme are first discussed, pointing out the relevant role played by the polycrystalline nature of the string silicon channels on current transport. Starting from that, experimental data for RTN in 3D arrays are presented and explained via theoretical and simulation models. The attention is drawn, in particular, to the changes in the RTN dependences on the array working conditions that resulted from the transition from planar to 3D architectures. Such changes are explained by considering the impact of highly-defective grain boundaries on percolative current transport in cell channels in combination with the localized nature of the RTN traps.

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Section: Experimental Datasupporting

confidence: 86%

“…This kind of fluctuations in poly-Si channels were first shown (to our knowledge) in [ 118 ], on a nanowire structure (no filler oxide), showing an exponential distribution for

law, and can be effectively characterized by the slope

of the exponential distribution.…”

Section: Experimental Datasupporting

confidence: 72%

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Random Telegraph Noise in 3D NAND Flash Memories

et al. 2021

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“…Statistical data for RTN are shown in [320][321][322] and are presented in Figure 38 (left) for different temperatures. Note that the usual exponential distribution of amplitude appears, whose slope is greatly reduced with respect to planar technologies [299,323,324].…”

Section: Random Telegraph Noisementioning

confidence: 99%

Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices

2017

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Abstract:We review the state-of-the-art in the understanding of planar NAND Flash memory reliability and discuss how the recent move to three-dimensional (3D) devices has affected this field. Particular emphasis is placed on mechanisms developing along the lifetime of the memory array, as opposed to time-zero or technological issues, and the viewpoint is focused on the understanding of the root causes. The impressive amount of published work demonstrates that Flash reliability is a complex yet well-understood field, where nonetheless tighter and tighter constraints are set by device scaling. Three-dimensional NAND have offset the traditional scaling scenario, leading to an improvement in performance and reliability while raising new issues to be dealt with, determined by the newer and more complex cell and array architectures as well as operation modes. A thorough understanding of the complex phenomena involved in the operation and reliability of NAND cells remains vital for the development of future technology nodes.

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“…For instance, any variations in the number of carriers or structural defects have a much larger impact on the output and performance in a scaled device, and the effects of device scaling on variability due to RDF and gate line-edge roughness (LER) have also been reported [2][3][4]. Random telegraph noise (RTN) is thought to be another major challenge for devices with small area, such as NAND Flash and RRAMs [5][6][7][8][9][10][11]. In this work, we investigate the RTN noise in an n-channel FinFET-based FIND RRAM cell, which has already been successfully implemented in standard logic process in 1kbit arrays [12].…”

Section: Introductionmentioning

confidence: 99%

RTN and Annealing Related to Stress and Temperature in FIND RRAM Array

2019

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In this work, an observation on random telegraph noise (RTN) signal in the read current of a FinFET dielectric RRAM (FIND RRAM) device is presented. The RTN signal of a FIND RRAM cell is found to change after the device being subjected to cycling stress. After undergoing cycling stress, RRAM cells have a stronger tendency to show more frequent and intense RTN signals. The increase of noise levels in FIND RRAM cells can be alleviated generally by high temperature anneal, and with this concept, an on chip annealing scheme is proposed and demonstrated.

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Poly-Silicon Trap Position and Pass Voltage Effects on RTN Amplitude in a Vertical NAND Flash Cell String

Cited by 17 publications

References 10 publications

Random Telegraph Noise in 3D NAND Flash Memories

Random Telegraph Noise in 3D NAND Flash Memories

Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices

RTN and Annealing Related to Stress and Temperature in FIND RRAM Array

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