Poly-Si gate patterning issues for ultimate MOSFET

Louis, D.; Nier, M.E.; Fery, C.; Heitzmann, M.; Papon, A.M.; Renard, S.

doi:10.1016/s0167-9317(02)00437-9

Cited by 6 publications

(4 citation statements)

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“…The other is that Poly B provides a straight poly profile after etching because the straight poly profile results in better I dsat -I off characteristics than the notch poly profile. 16,17 For the 65 nm node and beyond, the V ccគmin of the SRAM has been widely discussed, and the static noise margin is strongly correlated to the V ccគmin . 18 In this study, the 0.525 m 2 cell size 6T-…”

Section: Resultsmentioning

confidence: 99%

Improved Poly Gate Engineering for 65 nm Low Power CMOS Technology

Chen

et al. 2010

J. Electrochem. Soc.

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A design for the polycrystalline gate is developed for 65nm low power complementary metal oxide semiconductor (CMOS) technology. Using the poly deposition, a less poly depletion effect and a decrease in the electrical gate dielectric thickness (Tox) can be obtained. Also, the poly deposition successfully reduces the roughness of the poly surface and produces a smaller poly grain size after subsequent rapid thermal processing steps. Meanwhile, the poly deposition can suppress the short channel effect and can reduce off-state leakage current. The poly deposition results in better voltage ramp dielectric breakdown and uniformity on a specific test vehicle. The Idsat asymmetry characteristics of the device are also improved by the poly deposition. The Vcc̱min of the 0.525μnormalm2 cell size 6T-static random access memory using the poly deposition is also improved due to leakage current reduction and well Idsat asymmetry.

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Section: Resultsmentioning

confidence: 99%

Improved Poly Gate Engineering for 65 nm Low Power CMOS Technology

Chen

et al. 2010

J. Electrochem. Soc.

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“…5 This also requires various attempts to develop small gate patterning technology. 8 Critical dimension ͑CD͒ gain was reported during plasma etching due to the sloped profile of PR by erosion, PR swelling, and redeposition with PR mask. 8 Critical dimension ͑CD͒ gain was reported during plasma etching due to the sloped profile of PR by erosion, PR swelling, and redeposition with PR mask.…”

Section: Introductionmentioning

confidence: 99%

“…8 Critical dimension ͑CD͒ gain was reported during plasma etching due to the sloped profile of PR by erosion, PR swelling, and redeposition with PR mask. 8 Therefore, it becomes evi-dent that a hard mask is urgently required to overcome these challenges. 8 Therefore, it becomes evi-dent that a hard mask is urgently required to overcome these challenges.…”

Section: Introductionmentioning

confidence: 99%

“…Etching properties of poly-Si with hard masks are well understood, 8 whereas etching properties of metal with hard masks have hardly been discussed. The introduction of both a hard mask and a metal electrode in the gate stacks poses new challenges in the etching process, because nonvolatile by-products are generated more during the etching of metals than poly-Si and the etch rates of metals are lower than that of poly-Si.…”

Section: Introductionmentioning

confidence: 99%

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Effects of SiO2∕Si3N4 hard masks on etching properties of metal gates

Hwang

Cho

Chan

et al. 2006

Journal of Vacuum Science &Amp; Technology B: Microelectronics and Nanometer Structures Processing, Measurement, and Phenomena

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Articles you may be interested inEffects of fluorine incorporation and forming gas annealing on high-k gated germanium metal-oxidesemiconductor with Ge O 2 surface passivation Appl. Phys. Lett. 93, 073504 (2008); 10.1063/1.2966367 On the dc and noise properties of the gate current in epitaxial Ge p -channel metal oxide semiconductor field effect transistors with Ti N ∕ Ta N ∕ Hf O 2 ∕ Si O 2 gate stack Investigation of etching properties of metal nitride/high-k gate stacks using inductively coupled plasma J. Vac. Sci. Technol. A 23, 964 (2005); 10.1116/1.1927536Physical and electrical properties of metal gate electrodes on HfO 2 gate dielectrics Reduced etching rates of advanced metal gates ͑TaN, TiN, and HfN͒ using SiO 2 /Si 3 N 4 hard masks are observed in Cl 2 plasma. Si and O released from hard masks react with metal surfaces newly exposed to the plasma during the etching, thereby forming metal oxides. The metal oxides formed on the etched surface retard the etch rates. The suppression of etch rates with hard mask is more obvious for TiN than for TaN and HfN, because Ti oxides are readily formed on the etched TiN surface due to their low Gibbs free energies of formation. The surface of TiN degrades with etching time with SiO 2 mask, because etching rates of Si oxides and Ti oxides are different in the ͑TiO 2 ͒ 1−x ͑SiO 2 ͒ x residues remaining on the etched surface. In contrast, a conventional poly-Si electrode does not show the mask effects on etch rates and surface roughness.

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