Effects of SiO2∕Si3N4 hard masks on etching properties of metal gates

Abstract

Articles you may be interested inEffects of fluorine incorporation and forming gas annealing on high-k gated germanium metal-oxidesemiconductor with Ge O 2 surface passivation Appl. Phys. Lett. 93, 073504 (2008); 10.1063/1.2966367 On the dc and noise properties of the gate current in epitaxial Ge p -channel metal oxide semiconductor field effect transistors with Ti N ∕ Ta N ∕ Hf O 2 ∕ Si O 2 gate stack Investigation of etching properties of metal nitride/high-k gate stacks using inductively coupled plasma J. Vac. Sci. Technol. A 23, 964 (2005); 10.1116/1.1927536Physical and electrical properties of metal gate electrodes on HfO 2 gate dielectrics Reduced etching rates of advanced metal gates ͑TaN, TiN, and HfN͒ using SiO 2 /Si 3 N 4 hard masks are observed in Cl 2 plasma. Si and O released from hard masks react with metal surfaces newly exposed to the plasma during the etching, thereby forming metal oxides. The metal oxides formed on the etched surface retard the etch rates. The suppression of etch rates with hard mask is more obvious for TiN than for TaN and HfN, because Ti oxides are readily formed on the etched TiN surface due to their low Gibbs free energies of formation. The surface of TiN degrades with etching time with SiO 2 mask, because etching rates of Si oxides and Ti oxides are different in the ͑TiO 2 ͒ 1−x ͑SiO 2 ͒ x residues remaining on the etched surface. In contrast, a conventional poly-Si electrode does not show the mask effects on etch rates and surface roughness.

Electrical characteristics of multi-gate P-channel FinFETs with V<inf>T</inf> implanting energies under temperature stress

“…With incorporating oxidation-and-etch process steps integrating the oxidation plus the nitridation film as a hard mask [3], the top feature size of device on wafer can be controlled to 80-90 nm. The last oxidation process was chosen to gain an appropriate oxide layer for the subsequent Si-fin hard mask definition to obtain a desirable Si-fin width such as 11-27 nm.…”

Modeling and simulation of coverage and film properties in deposition process on large-scale pattern using statistical ensemble method

“…SiN films deposited at a process temperature of approximately 400 °C are widely used as mask materials for gate electrode etching and self-aligned patterning, a stressor for side walls, etch stoppers for SiO 2 contact hole etching, and passivation layers in various CMOS devices. [18][19][20][21][22][23][24][25][26][27][28][29][30][31][32][33][34][35][36] Recently, the stacking of such films with organic films has yielded various devices, for example, virtual reality goggles, smartwatches, and displays for the Internet of Things, 37,38) thereby necessitating a lower process temperature of approximately 100 °C. The experiments for the plasma-enhanced chemical vapor deposition (PECVD) process using a SiH 4 /NH 3 /N 2 gas mixture at a wafer temperature of 120 °C revealed a characteristic variation between the SiN morphology and film density.…”

Ta/TiN midgap full-metal single gate fabrication using combined chlorine-based plasma and highly selective chemical metal etching for decananometer CMOS technology

“…In that context, the integration of a full metal gate naturally emerges as the ideal option which is, however, hindered by difficult problems associated to low etching selectivity with respect to the photoresist mask and underlying dielectric materials [6]. Furthermore, metal etching also raises other challenges due to the generation of non volatile residues, anomalous edge roughening and notching [7,8]. In this paper, a two-step dry and wet etching strategy that produces vertical roughness-free sidewalls and features an ultra high etch rate selectivity (>500) between the metal and the oxide is demonstrated.…”