Poly/high-k/SiON gate stack and novel profile engineering dedicated for ultralow-voltage silicon-on-thin-BOX (SOTB) CMOS operation

Yamamoto, Y.; Makiyama, Hideki; Tsunomura, T.; Iwamatsu, T.; Oda, H.; Sugii, Nobuyuki; Yamaguchi, Yasuo; Mizutani, Tomoko; Hiramoto, Toshiro

doi:10.1109/vlsit.2012.6242485

Cited by 23 publications

(25 citation statements)

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“…For breaking through the tight trade-off between active (operation) and standby (leakage) current of transistors to reduce total current consumption, SOI (Silicon on Insulator) based process technologies are considered as good candidates. SOTB process [26], [27] is one of the most promising among them and actual shipment of products developed with SOTB process has been already started [28]. As summarized in Fig.…”

Section: Extremely Low Energy Solution With Sotb (Silicon On Thin Burmentioning

confidence: 99%

Essential Roles, Challenges and Development of Embedded MCU Micro-Systems to Innovate Edge Computing for the IoT/AI Age

Kimura

Taito

Hidaka

2020

IEICE Trans. Electron.

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Embedded system approaches to edge computing in IoT implementations are proposed and discussed. Rationales of edge computing and essential core capabilities for IoT data supply innovation are identified. Then, innovative roles and development of MCU and embedded flash memory are illustrated by technology and applications, expanding from CPS to big-data and nomadic/autonomous elements of IoT requirements. Conclusively, a technology roadmap construction specific to IoT is proposed.

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Section: Extremely Low Energy Solution With Sotb (Silicon On Thin Burmentioning

confidence: 99%

Essential Roles, Challenges and Development of Embedded MCU Micro-Systems to Innovate Edge Computing for the IoT/AI Age

Kimura

Taito

Hidaka

2020

IEICE Trans. Electron.

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“…thin BOX layer and doped ground plane (n GP and p GP) just below the BOX layer; (iii) flexible V th tuning by impurity density control of the ground plane and (iv) high design compatibility with the conventional CMOS due to mostly identical planar layout to the bulk and a hybrid bulk integration for I/O. Details of the SOTB fabrication process are reported elsewhere [15,16]. Figure 3.…”

Section: Sotb Device Technologymentioning

confidence: 99%

“…V th control optimized for the ULV operation has been an important process issue. In this optimization, we controlled the V th values at around 0.2 V, which is by about 0.2 V lower than that for the low-standby-power (LSTP) application, with the multiple V th option utilizing a poly-silicon and high-k gate-stack technology and a proper doping profile control of the ground plane [15]. As shown in Figure 4, we utilize a small amount of high-k (Hf and Al) oxide mixed with the conventional SiON gate dielectric and control proper effective work function (EWF) both for NMOS and PMOS.…”

Section: Sotb Device Technologymentioning

confidence: 99%

“…We hypothesize the main issues for the highly energy efficient CMOS circuits are adaptive V th control and small variability, as described in this section. In order to solve these issues, we are developing the silicon on thin buried oxide (SOTB) [12][13][14][15][16]. In this article, we show SOTB's low voltage capability, including small variability and back-bias control through device and circuit results.…”

Section: Introduction: Issues For Ulv Operation Possibly Staying On Mmentioning

confidence: 99%

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Ultralow-Power SOTB CMOS Technology Operating Down to 0.4 V

Sugii

Yamamoto

Makiyama

et al. 2014

JLPEA

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Ultralow-voltage (ULV) CMOS will be a core building block of highly energy efficient electronics. Although the operation at the minimum energy point (MEP) is effective for ULP CMOS circuits, its slow operation speed often means that it is not used in many applications. The silicon-on-thin-buried-oxide (SOTB) CMOS is a strong candidate for the ultralow-power (ULP) electronics because of its small variability and back-bias control. Proper power and performance optimization with adaptive V th control

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“…We choose poly-silicon/high-k/SiON gate stack because it has adequate EWF (around quarter gap) for the ULV operation and its fabrication process is cost effective. Moreover, we implemented a novel impurity-profile engineering named local ground plane (LGP) (9) to improve the V th controllability, drain parasitic capacitance, and robustness against the gate-length variation. As shown in Fig.…”

Section: Transistor Optimization For Ulv Operationmentioning

confidence: 99%

(Invited) Silicon on Thin Buried Oxide (SOTB) Technology for Ultralow-Power Applications

Sugii¹,

Iwamatsu²,

Yamamoto³

et al. 2013

ECS Trans.

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Demands for low-power CMOS devices are still increasing. Ultralow-voltage operation of CMOS with maximum power efficiency can extend the opportunity of using the electron devices to power-conscious applications such as ubiquitous sensor network, etc. The main issues for low-power (highly efficient) operation of the modern scaled CMOS are reducing variability and enabling adaptive control of circuit performance and power consumption under the operation at voltages as low as possible. In order to solve these issues, we are developing the silicon-on-thin-buried-oxide (SOTB) transistors. We show features of the SOTB, transistor technology dedicated for ultralow-voltage (down to 0.4 V) operation, circuit design applicable for SOTB and we discuss on the performance projection and ULV application with SOTB.

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Poly/high-k/SiON gate stack and novel profile engineering dedicated for ultralow-voltage silicon-on-thin-BOX (SOTB) CMOS operation

Cited by 23 publications

References 0 publications

Essential Roles, Challenges and Development of Embedded MCU Micro-Systems to Innovate Edge Computing for the IoT/AI Age

Essential Roles, Challenges and Development of Embedded MCU Micro-Systems to Innovate Edge Computing for the IoT/AI Age

Ultralow-Power SOTB CMOS Technology Operating Down to 0.4 V

(Invited) Silicon on Thin Buried Oxide (SOTB) Technology for Ultralow-Power Applications

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