Polarity control of carrier injection for nanowire feedback field-effect transistors

Lim, Doohyeok; Kim, Sangsig

doi:10.1007/s12274-019-2477-6

Cited by 29 publications

(35 citation statements)

References 21 publications

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“…Mixtures of complementary DNA-functionalized nanoparticles (NPs) that vary in size and DNA surface density were assembled and characterized by means of electron microscopy, synchrotron small-angle x-ray scattering (SAXS), and scale-accurate molecular dynamics (MD) simulations with explicit hybridization (17,25,26). Through a combination of theory, simulations, and experiments, we show that small particles grafted with low numbers of DNA strands (for example, <6), when mixed with complementary functionalized NPs (Fig.…”

mentioning

confidence: 99%

Particle analogs of electrons in colloidal crystals

Girard

Wang

et al. 2019

Science

102

132

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A versatile method for the design of colloidal crystals involves the use of DNA as a particle-directing ligand. With such systems, DNA-nanoparticle conjugates are considered programmable atom equivalents (PAEs), and design rules have been devised to engineer crystallization outcomes. This work shows that when reduced in size and DNA grafting density, PAEs behave as electron equivalents (EEs), roaming through and stabilizing the lattices defined by larger PAEs, as electrons do in metals in the classical picture. This discovery defines a new property of colloidal crystals—metallicity—that is characterized by the extent of EE delocalization and diffusion. As the number of strands increases or the temperature decreases, the EEs localize, which is structurally reminiscent of a metal-insulator transition. Colloidal crystal metallicity, therefore, provides new routes to metallic, intermetallic, and compound phases.

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mentioning

confidence: 99%

Particle analogs of electrons in colloidal crystals

Girard

Wang

et al. 2019

Science

102

132

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Section: Introductionmentioning

confidence: 99%

“…[15] However, electrostatic doping induced by gate bias is required to form a potential well, which is important for the positive feedback loop. [16,17] Although thyristor RAMs (T-RAMs) employ doping regions to form the potential well, external bias is still necessary for T-RAMs to retain the stored charges. [18][19][20] This indispensable bias for holding the stored charges has restricted their use in quasi-nonvolatile memory applications.In this paper, we propose a fully CMOS-compatible p + -n-pn + silicon memory device to enable quasi-nonvolatile memory functionality with high speed, long retention time, and nondestructive reading capability.…”

mentioning

confidence: 99%

Quasi‐Nonvolatile Silicon Memory Device

Lim

Son

Cho

2020

Adv Materials Technologies

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Several attempts have been made to store charges in the channel regions of silicon transistors, such as in zero-capacitor random-access memories (Z-RAMs), [7,8] metastable DRAMs (MSDRAMs), [9,10] advanced RAMs (A-RAMs), [11,12] and zeroslope and zero-impact ionization RAMs (Z 2-RAMs). [13,14] Among these, Z 2-RAMs are capable of low-voltage operation with high speed, long retention time, and nondestructive reading capability, because of the positive feedback loop. [15] However, electrostatic doping induced by gate bias is required to form a potential well, which is important for the positive feedback loop. [16,17] Although thyristor RAMs (T-RAMs) employ doping regions to form the potential well, external bias is still necessary for TRAMs to retain the stored charges. [18-20] This indispensable bias for holding the stored charges has restricted their use in quasi-nonvolatile memory applications. In this paper, we propose a fully CMOS-compatible p +-n-pn + silicon memory device to enable quasi-nonvolatile memory functionality with high speed, long retention time, and nondestructive reading capability. Using a well-defined potential well in a p +-n-p-n + silicon structure with a gated n-channel region, our device utilizes holes as majority charge carriers for the positive feedback loop, unlike TRAMs which use electrons as majority charge carriers. Hence, our quasi-nonvolatile silicon memory device can retain the charges stored in the channel region without requiring any external bias, for a long time. In addition, the positive-feedback loop enables low-voltage operation, high speed, and nondestructive reading for quasi-nonvolatile memory applications. 2. Results and Discussion A quasi-nonvolatile silicon memory device consists of p +-n-p-n + regions on a silicon-on-insulator (SOI) substrate (Figure 1a). An SiO 2 /poly-Si gate stack is located on the upper side of the n-channel region. The poly-Si gate modulates the potential barrier of the n-channel region; it controls the hole injection from the p + drain region. The p-channel region is designated to block the electron injection from the n + source region. The channel regions also form potential wells; states "1" and "0" are defined by presence and absence of excess charge carriers in the potential wells, respectively. The corresponding energy band diagrams exhibit the difference in the channel region between the two states (Figure 1b). Barrier-height modulation by carrier accumulation in the potential wells is essential for the positive feedback loop, which allows memory operations. Memory hierarchy among conventional memory technologies is one of the main bottlenecks in modern computer systems; alternative memory technologies are thus necessary for quasi-nonvolatile memory applications. Herein, a fully complementary metal-oxide-semiconductor-compatible quasi-nonvolatile memory composed of p +-n-p-n + silicon on a silicon-on-insulator substrate is presented. The quasi-nonvolatile silicon memory device demonstrates highspeed write capability (≤100 ns), long retenti...

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“…Feedback field-effect transistors (FBFETs) have attracted significant attention as promising next-generation transistors owing to their low subthreshold swing ( SS ), high on/off-current ratio, and low operating voltage 1 – 6 . Their operating mechanism is based on a positive feedback loop that modulates the height of the potential barriers in the channel region 1 – 6 . Most FBFET designs have complex fabrication procedures 1 , 2 , or additional gate electrodes 3 , 5 , 6 .…”

Section: Introductionmentioning

confidence: 99%

“…Their operating mechanism is based on a positive feedback loop that modulates the height of the potential barriers in the channel region 1 – 6 . Most FBFET designs have complex fabrication procedures 1 , 2 , or additional gate electrodes 3 , 5 , 6 . Recently, single gate-all-around (GAA) FBFETs with p + - n + - i - n + Si nanowire (SiNW) channels have been proposed to reduce complex device structures and additional gate electrodes 4 .…”

Section: Introductionmentioning

confidence: 99%

Simulation studies on electrical characteristics of silicon nanowire feedback field-effect transistors with interface trap charges

Yang

Park

Son

et al. 2021

Sci Rep

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In this study, we examine the electrical characteristics of silicon nanowire feedback field-effect transistors (FBFETs) with interface trap charges between the channel and gate oxide. The band diagram, I–V characteristics, memory window, and operation were analyzed using a commercial technology computer-aided design simulation. In an n-channel FBFET, the memory window narrows (widens) from 5.47 to 3.59 V (9.24 V), as the density of the positive (negative) trap charges increases. In contrast, in the p-channel FBFET, the memory window widens (narrows) from 5.38 to 7.38 V (4.18 V), as the density of the positive (negative) trap charges increases. Moreover, we investigate the difference in the output drain current based on the interface trap charges during the memory operation.

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Polarity control of carrier injection for nanowire feedback field-effect transistors

Cited by 29 publications

References 21 publications

Particle analogs of electrons in colloidal crystals

Particle analogs of electrons in colloidal crystals

Quasi‐Nonvolatile Silicon Memory Device

Simulation studies on electrical characteristics of silicon nanowire feedback field-effect transistors with interface trap charges

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