PLL charge pump with adaptive body-bias compensation for minimum current variation

Liu, P.; Sun, Pinping; Jung, Jean; Heo, Deukhyoun

doi:10.1049/el.2011.2835

Cited by 25 publications

(20 citation statements)

References 5 publications

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“…One of the most important components of the PLL is the charge pump circuit. An adaptive body bias charge pump circuit is proposed in [11]. In this circuit a number of resistances are used to compensate current variation.…”

Section: Proposed Charge Pump Circuitmentioning

confidence: 99%

A Low Noise, Low Power Phase-Locked Loop, Using Optimization Methods

Ghaderi

Erfani-Jazi

Mohseni-Mirabadi

2016

Journal of Electrical and Computer Engineering

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A divider-less, low power, and low jitter phase-locked loop (PLL) is presented in this paper. An extra simple open loop phase frequency detector (PFD) is proposed which reduces the power consumption and increases the overall speed. A novel bulk driven Wilson charge pump circuit, whose performance is enhanced by some optimization algorithms, is also introduced to get high output swing and high current matching. The designed PLL is utilized in a0.18 μmCMOS process with a 1.8 V power supply. It has a wide locking range frequency of 500 MHz to 5 GHz. In addition, through the use of a dead-zone-less PFD and a divider-less PLL, the overall jitter is decreased significantly.

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Section: Proposed Charge Pump Circuitmentioning

confidence: 99%

A Low Noise, Low Power Phase-Locked Loop, Using Optimization Methods

Ghaderi

Erfani-Jazi

Mohseni-Mirabadi

2016

Journal of Electrical and Computer Engineering

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“…It is usually implemented with charge pump circuits. Since the charge pump circuits are suitable for integration, they have become a focal point in researches such as Bian, Yao, and Luo (2012), Leung, Sun, Leung, andOr (2011), Liu, Sun, Jung, andHeo (2012). The operation of FVC is described in detail in Djemouai et al (2001).…”

Section: Principle Of Process and Temperature Compensationmentioning

confidence: 99%

Process, voltage and temperature compensation in a 1-MHz 130nm CMOS monolithic clock oscillator with 2.3% accuracy

Bian

Yao

2014

International Journal of Electronics

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This paper presents an on-chip process, voltage and temperature (PVT) compensation technique for a 1-MHz monolithic clock oscillator in a CMOS process. The oscillator is based on carrier mobility and frequency-to-voltage converter (FVC), which is based on charge pump circuit. An adaptive charge current maintains a constant frequency without trimming. Furthermore, a reference voltage with a second-order temperature coefficient further compensates the variation of frequency with temperature. It improves the accuracy of existing carrier-mobility-based oscillator, from 4.5% to 2.3%. The circuit was designed in a 130 nm CMOS 3.3 V device process. The results show that the output frequency is within AE 2.3% variation in the worst case. The variations of frequency with process, temperature (−40 to 125°C) and power supply are within AE 1.8%, AE 0.8% and AE 0.2%/V, respectively. It achieves a CMOS monolithic clock oscillator insensitive to PVT.

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“…In order to minimize the variation of the current over a wide range of output voltage a charge pump designed by Liu et al [6] has been implemented. Here the charge pump loop bandwidth remains constant.…”

Section: Introductionmentioning

confidence: 99%

Study of Recent Charge Pump Circuits in Phase Locked Loop

Nanda¹,

Sarangi²,

Rout³

2016

IJMECS

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This paper reviews the design of phase locked loop (PLL) using recently reported charge pump circuits. Lock time, phase noise, lock range and reference spur of each charge pump circuit are investigated. Though improved charge pump circuits are designed recently, their performance is not as effective as the basic charge pump PLL (CP-PLL). Initially the design of PLL using the basic charge pump is completed in this paper and then the PLL using improved charge pumps are redesigned in CMOS 180 nm technology and simulated using Cadence Virtuoso Analog Design Environment. Finally all the charge pumps are compared with respect to the PLL performances. The current starved voltage controlled oscillator (VCO) used for the design of PLL brings about a tuning range of 119.5 MHz to 2.3 GHz. The PLL using different charge pumps produces a lock time which varies from 204 ns to 329 ns. The other parameters like lock range, phase noise and reference spur are also examined. Index Terms-Lock in time, lock range, phase noise, Phase locked loop (PLL), reference spur, Voltage controlled oscillator (VCO).

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PLL charge pump with adaptive body-bias compensation for minimum current variation

Cited by 25 publications

References 5 publications

A Low Noise, Low Power Phase-Locked Loop, Using Optimization Methods

A Low Noise, Low Power Phase-Locked Loop, Using Optimization Methods

Process, voltage and temperature compensation in a 1-MHz 130nm CMOS monolithic clock oscillator with 2.3% accuracy

Study of Recent Charge Pump Circuits in Phase Locked Loop

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