PLL based high speed functional testing

Jayabalan,; Goh, Chee Kiang; Leong, Ooi Ban; Seng, Leong Mook; Iyer,; Tay, A.A.O.

doi:10.1109/ats.2003.1250794

Cited by 8 publications

(2 citation statements)

References 3 publications

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“…On the other hand, closeness of the wire traces makes the circuits vulnerable to strong coupling of the noise in the high-speed clock lines. So jitter tolerance is a necessity in such designs [12].…”

Section: Functional Test Featuresmentioning

confidence: 99%

See 1 more Smart Citation

A Novel Test Strategy for Fine Pitch Wafer-Level Packaged Devices

Jayabalan

Rotaru

Rao

et al. 2007

IEEE Trans. Adv. Packag.

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This paper describes an innovative test strategy comprising a compliant elastomer mesh for testing fine pitch wafer-level package (WLP) devices. The test probe, hardware, and sample preparation processes are detailed. The components of the test hardware socket such as the SMA connectors, coplanar transmission lines on the PCB, via, off-chip interconnect, and elastomer mesh probe have been modeled. A complete system-level model, with off-chip interconnects on the WLP device pads, has been developed. The measurement and model demonstrate that the prototype test socket performs at 5 GHz with an insertion loss of about 3 dB. WLP device with Bed-of-Nail interconnects are characterized. Functional test features of the system are also addressed.Index Terms-Coplanar probe, elastomer mesh substrate, multigigahertz test, wafer-level package test and characterization.

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Section: Functional Test Featuresmentioning

confidence: 99%

“…However, for functional testing of devices at wafer level, the multigigahertz signal is generated by multiplexing a low-frequency clock from an external RF source in a programmable gate array chip [5] or a phase-locked loop chip [12], which is placed close to the DUT probe (Fig. 18).…”

Section: Functional Test Featuresmentioning

confidence: 99%