Platform-Based Behavior-Level and System-Level Synthesis

Abstract

Abstract-With the rapid increase of complexity in Systemon-a-Chip (SoC) design, the electronic design automation (EDA) community is moving from RTL (Register Transfer Level) synthesis to behavioral-level and system-level synthesis. The needs of system-level verification and software/hardware codesign also prefer behavior-level executable specifications, such as C or SystemC. In this paper we present the platform-based synthesis system, named xPilot, being developed at UCLA. The first objective of xPilot is to provide novel behavioral synthesis capability for automatically generating efficient RTL code from a C or SystemC description for a given system platform and optimizing the logic, interconnects, performance, and power simultaneously. The second objective of xPilot is to provide a platform-based system-level synthesis capability, including both synthesis for application-specific configurable processors and heterogeneous multi-core systems. Preliminary experiments on FPGAs demonstrate the efficacy of our approach on a wide range of applications and its value in exploring various design tradeoffs. I. MOTIVATIONThe relentless tracking of Moore's curve by the entire semiconductor industry has showcased the exponential scaling of the transistor feature size by a factor of 0.7 reduction every three years. This leads to exponentially increasing transistor counts and results in an explosive growth in functionality and the amount of computing power available on a single chip. Today it is perfectly feasible to design a System-on-a-Chip (SoC) with one billion transistors [7], and it is generally believed that industry will continue to overcome technical hurdles to sustain this trend for another decade. However, the cost of developing these chips and providing production facilities is also growing at a very fast pace. For instance, the total development cost of a single complex, high-density SoC at today's 90-nm technology can easily be in the $20 to $30 million range. The ITRS 2005 edition [7] has also emphasized that the cost of design remains the greatest threat to continuation of the semiconductor roadmap.Unfortunately, the progress of design technologies lags behind that of process manufacturing technologies. The constantly improving CAD tools can help to mitigate the problem by delivering faster simulation, higher capacity formal verification, and better logic synthesis coupled with place-androute. However, these improvements fail to close the design productivity gap, i.e., the number of available transistors grows faster than the ability to meaningfully design them.It is commonly acknowledged that the ultimate solution is to move to the next level of abstraction beyond RTL, and Electronic system-level (ESL) design automation has been widely identified as the next productivity boost for the semiconductor industry. However, despite some recent success in ESL simulation, the transition to ESL design will not be as well accepted as the transition to RTL without robust and efficient behavior-level and system-level syn...

Behavioral synthesis with activating unused flip-flops for reducing glitch power in FPGA

“…We incorporated our scheduling and binding techniques into the behavioral synthesis tool, xPilot, introduced in [8]. In this section we will compare the power efficiency of the RTL designs generated by the conventional behavioral synthesis [8] and by our firewall-register-supporting (FRsupporting) behavioral synthesis.…”

“…In this section we will compare the power efficiency of the RTL designs generated by the conventional behavioral synthesis [8] and by our firewall-register-supporting (FRsupporting) behavioral synthesis.…”

“…Here the resource constraints are 20% of the total number of the operations in a DFG. Columns 4 to 6 show the results from the conventional synthesis flow presented in [8]. Columns 7 to 9 present the results from the conventional flow with firewall register insertion; i.e., we still use the conventional scheduling and binding algorithms but additionally insert firewall registers.…”

“…Conventional flow [8] Conventional flow [8] 833 146 772 828 128 788 919 119 DIF 6 2 788 987 174 852 988 155 916 1029 126 DIT 7 3 932 1214 199 1012 1173 202 1076 1296 140 LEE 6 4 1028 1126 174 1092 1132 158 1172 1156 115 MCM 13 6 1652 2085 241 1956 2261 243 1940 2225 220 WANG 5 4 836 998 204 916 1025 144 980 1065 133 CHEM 33 33 5076 6063 719 5892 6126 553 5716 5330 556 DIR 11 12 1732 2091 275 2084 2156 195 2100 2152 160 HONDA 9 10 1364 1768 223 1668 1741 175 1668 1764 166 PR 5 3 548 859 137 612 872 101 …”

Multilevel Granularity Parallelism Synthesis on FPGAs

“…Ongoing developments in the field of high-level synthesis (HLS) have led to the emergence of several industry [1][2][3] and academia powered [4,5] tools that can generate device-specific RTL descriptions from popular High-Level programming Languages (HLLs). Such tools help raise the abstraction of the programming model and constitute a significant improvement in FPGAs' usability.…”