Plasma-Charging Damage of Floating MIM Capacitors

Wang, Zhichun; Ackaert, J.; Salm, Cora; Kuper, F.G.; Tack, M.; Backer, E. De; Coppens, P.; Schepper, L. De; Vlachakis, B.

doi:10.1109/ted.2004.829518

Cited by 22 publications

(7 citation statements)

References 18 publications

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“…For transistors with t ox ¼ 3:5 nm, the AR CTM dependence of the NBTI degradation follows a power-law relationship consistent with eq. (8). It further demonstrates that both the model and the experimental data show a power-law relationship between the NBTI lifetime and AR CTM with m ¼ À0:3.…”

Section: Results For Degradation Of Transistor Reliabilitymentioning

confidence: 58%

“…From eqs. (4)- (8), one can predict the functional dependence of the NBTI degradation on plasma damage and the design parameters of AR CTM and t ox . However, the amount of plasma damage may vary among transistors owing to different plasma conditions and values of AR CTM , and t ox due to variations during processing.…”

Section: Prediction Of Transistor Reliability Failure Distributionmentioning

confidence: 99%

“…The NBTI lifetime is affected by the variation in ÁN it from eqs. ( 6)- (8). By assuming a nominally identical AR CTM and t ox , and with the further assumption of a normal distribution of ÁN it ð; Þ, a corresponding distribution of threshold voltage shift will be generated during NBTI stressing.…”

Section: Prediction Of Transistor Reliability Failure Distributionmentioning

confidence: 99%

“…Although subsequent annealing can eliminate the effects of P 2 ID, weak points in the bulk oxide and the SiO 2 /Si substrate interface resulting from P 2 ID can further degrade the transistor reliability after reliability stressing. Although the P 2 ID-enhanced degradation in reliability of a single MOSFET 7) or a stand-alone metal-insulator-metal (MIM) capacitor 8) has been previously studied, there have been no studies on this issue for circuits comprising both MOSFETs and MIM capacitors.…”

Section: Introductionmentioning

confidence: 99%

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Effects of Plasma Damage on Metal–Insulator–Metal Capacitors and Transistors for Advanced Mixed-Signal/Radio-Frequency Metal–Oxide–Semiconductor Field-Effect Transistor Technology

Weng¹,

Lee

Lin³

et al. 2009

Jpn. J. Appl. Phys.

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The effects of damage on mixed-signal (MS)/radio-frequency (RF) circuits integrated with metal-insulator-metal (MIM) capacitors and advanced metal-oxide-semiconductor field-effect transistors (MOSFETs) are studied in this work. The impact of damage on an MIM oxide is evaluated by connecting its capacitor top metal (CTM) to an upper-level metal with a large antenna ratio (AR CTM) used in an actual CTM circuit connected to an interconnect. In addition to the dielectric degradation of a transistor, we also investigate the damage-enhanced negative bias temperature instability (NBTI) degradation of a transistor with its gate electrode connected to an MIM capacitor with a large AR CTM for various gate oxide thicknesses. A model is proposed to explain the experimentally observed dependence of NBTI degradation on AR CTM and accurately simulate failure distributions in the presence of plasma damage.

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Section: Results For Degradation Of Transistor Reliabilitymentioning

confidence: 58%

Section: Prediction Of Transistor Reliability Failure Distributionmentioning

confidence: 99%

Section: Prediction Of Transistor Reliability Failure Distributionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Effects of Plasma Damage on Metal–Insulator–Metal Capacitors and Transistors for Advanced Mixed-Signal/Radio-Frequency Metal–Oxide–Semiconductor Field-Effect Transistor Technology

Weng¹,

Lee

Lin³

et al. 2009

Jpn. J. Appl. Phys.

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“…There are many mechanisms by which reliability is affected. These are: (a) charging during dielectric deposition [2], (b) bottom plate roughness, and (c) dielectric thinning [3], [4], [5].…”

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confidence: 99%

Integrating TiN only bottom plate metal-insulator metal capacitor (MIMC) for contamination free manufacturing

Greenwood

Prasad

2007

2007 International Semiconductor Device Research Symposium

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Metal-Insulator-Metal Capacitors (MIMCs) are used in many modern analog capable CMOS processes. MIMCs feature high capacitance per unit area, low parasitic capacitance, due to their distance from substrate, and low 1st and 2nd order voltage coefficients [1].It is very important to have lower defect density to manufacture highly reliable analog devices. Current practice of integrating MIMC has high defect density and thus poor reliability. There are many mechanisms by which reliability is affected. These are: (a) charging during dielectric deposition [2], (b) bottom plate roughness, and (c) dielectric thinning [3], [4], [5].In this work, MIM capacitors are integrated in a high-voltage capable CMOS process flow. MIM capacitors used in this work have MIMC area per die above 3 million m 2 /die, thus reliability must be proven at this level to <1 ppm fails for this mode. The electrical requirements for the MIMC are 1.5fF/um^2 capacitance/area, 3.6V maximum operating voltage, and less than 30ppm 1st order voltage coefficient. The capacitor is integrated using 2nd layer metal, a silicon nitride (SiN) dielectric layer, and a special top plate metal (metal 2.5).In addition to the electrical requirements, the MIMC must also meet applications reliability requirements. The reliability of a MIMC is determined by MIMC area, voltage, and temperature. In the case of our current implementation that uses metal as a MIMC's bottom plate, we observe a population of MIMCs, which have lower than expected voltage breakdown (vbd)-the source of this is identified as a bottom plate roughness.In this paper, we report the integration of TiN only (with no Aluminum layer) as a bottom plate for MIMC to improve the defect density and thus the reliability. MIMC bottom plate surface roughnessThe characterization of the bottom plate roughness of a MIMC was performed by atomic force microscopy (AFM). The difference between the roughness of a standard metal bottom plate and the new TiN bottom plate are shown in Figures 1. respectively. These results are shown in Table 1. Figure 1: (a) AFM images of 'standard metal' bottom plate MIMC with a RMS value of 42.2 Å, (b) AFM images of a TiN only bottom plate showing improved surface roughness RMS value of 10.3 Å. Figures 1 (a) and (b) clearly shows that the surface roughness of a TiN only bottom plate is four times better than the standard metal bottom plate. 978-1-4244-1892-3/07/$25.00 ©2007 IEEE

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Chip Reliability

El-Kareh¹,

Hutter²

2015

Silicon Analog Components

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Plasma-Charging Damage of Floating MIM Capacitors

Cited by 22 publications

References 18 publications

Effects of Plasma Damage on Metal–Insulator–Metal Capacitors and Transistors for Advanced Mixed-Signal/Radio-Frequency Metal–Oxide–Semiconductor Field-Effect Transistor Technology

Effects of Plasma Damage on Metal–Insulator–Metal Capacitors and Transistors for Advanced Mixed-Signal/Radio-Frequency Metal–Oxide–Semiconductor Field-Effect Transistor Technology

Integrating TiN only bottom plate metal-insulator metal capacitor (MIMC) for contamination free manufacturing

Chip Reliability

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