Planarization Process Of Copper-polyimide Thin Film Multilayer Substrate

Abstract

We investigated a planarization process for the production of an MCM viapost interconnection type thin film multilayer substrate using resist as the planar sacnfical layer. The D.0.P (Degree of Planarization) of the polyimide and resist was investigated as a first step, and it was found that a higher D.O.P. was obtained by reducing the spin rotation and shortening the spin time of the spin coat. Next, the etching rate of the polyimide and resist were studied. It was found that when 0, gas was used the etching rate of the polyimide was faster than that of the resist, but that the etching rate of the polyimide was faster than that of the resist when CF, gas was used. We also found conditions at which the etching rate of the resist and polyimide were both at a maximum and at about the same Ievel. Wiring substrates were manufactured and subjected to temperature cycle test (-65 "C -+125 "C) to evaluate circuit connection reliability. The rate of change in connection resistance was less than +3% after IO00 test cycles, indicating an excellent substrate quality. The transmission characteristics of the stripline were also investigated.